公开(公告)号：US20050201193A1

公开(公告)日：2005-09-15

申请号：US11074897

申请日：2005-03-09

申请人： Naoki Kuroda ,  Yuji Nakai

发明人： Naoki Kuroda ,  Yuji Nakai

IPC分类号： G06F12/00 ,  G06F12/04 ,  G11C7/00 ,  G11C8/00 ,  G11C11/4063

CPC分类号： G11C7/10 ,  G11C7/1006 ,  G11C2207/107

摘要： A plurality of logic circuits both access the DRAM block by way of an access circuit. The operation clock for the DRAM block is set at a higher frequency than the system clock for the logic circuits. Outputs of a first bit width from the logic circuits are subjected to serial/parallel conversion into data of a second bit width and the data is written into the DRAM block.

摘要翻译： 多个逻辑电路都通过访问电路访问DRAM块。 DRAM块的操作时钟设置在比逻辑电路的系统时钟更高的频率上。 来自逻辑电路的第一位宽的输出经过串行/并行转换为第二位宽的数据，并将数据写入DRAM块。

公开(公告)号：US07057968B2

公开(公告)日：2006-06-06

申请号：US11075739

申请日：2005-03-10

申请人： Naoki Kuroda ,  Yuji Nakai

发明人： Naoki Kuroda ,  Yuji Nakai

IPC分类号： G11C8/00

CPC分类号： G11C11/413 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C11/412 ,  G11C2207/107

摘要： Logic circuits access a memory block by way of an access circuit. The memory block, which is formed of a mixed configuration of DRAMs and an SRAM, realizes the desired memory space. A data output register is provided at the output side of the SRAM so as to synchronize data output timing from the DRAMs with data output timing from the SRAM.

摘要翻译： 逻辑电路通过访问电路访问存储块。 由DRAM和SRAM的混合配置形成的存储器块实现期望的存储器空间。 在SRAM的输出侧提供数据输出寄存器，以使来自DRAM的数据输出定时与来自SRAM的数据输出定时同步。

公开(公告)号：US06990043B2

公开(公告)日：2006-01-24

申请号：US11074897

申请日：2005-03-09

申请人： Naoki Kuroda ,  Yuji Nakai

发明人： Naoki Kuroda ,  Yuji Nakai

IPC分类号： G11C8/18

CPC分类号： G11C7/10 ,  G11C7/1006 ,  G11C2207/107

摘要： A plurality of logic circuits access a DRAM block by way of an access circuit. The operation clock for the DRAM block is set at a higher frequency than the system clock for the logic circuits. Outputs of a first bit width from the logic circuits are subjected to serial/parallel conversion into data of a second bit width and the data is written into the DRAM block.

摘要翻译： 多个逻辑电路通过访问电路访问DRAM块。 DRAM块的操作时钟设置在比逻辑电路的系统时钟更高的频率上。 来自逻辑电路的第一位宽的输出经过串行/并行转换为第二位宽的数据，并将数据写入DRAM块。

公开(公告)号：US20050207266A1

公开(公告)日：2005-09-22

申请号：US11075739

申请日：2005-03-10

申请人： Naoki Kuroda ,  Yuji Nakai

发明人： Naoki Kuroda ,  Yuji Nakai

IPC分类号： G11C11/413 ,  G11C7/10 ,  G11C8/00 ,  G11C11/401 ,  G11C11/407 ,  G11C11/412

CPC分类号： G11C11/413 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C11/412 ,  G11C2207/107

摘要： Logic circuits access a memory block by way of an access circuit. The memory block, which is formed of a mixed configuration of DRAMs and an SRAM, realizes the desired memory space. A data output register is provided at the output side of the SRAM so as to synchronize data output timing from the DRAMs with data output timing from the SRAM.

摘要翻译： 逻辑电路通过访问电路访问存储块。 由DRAM和SRAM的混合配置形成的存储器块实现期望的存储器空间。 在SRAM的输出侧提供数据输出寄存器，以使来自DRAM的数据输出定时与来自SRAM的数据输出定时同步。

公开(公告)号：US06530253B1

公开(公告)日：2003-03-11

申请号：US09665080

申请日：2000-09-19

申请人： Masahiro Gotou ,  Masaki Nakajima ,  Yuji Nakai ,  Hideyuki Nagai ,  Daisuke Iwata ,  Naohisa Momiyama ,  Ken Shimizu ,  Masahiro Ishikawa ,  Tomohiro Sugiura

发明人： Masahiro Gotou ,  Masaki Nakajima ,  Yuji Nakai ,  Hideyuki Nagai ,  Daisuke Iwata ,  Naohisa Momiyama ,  Ken Shimizu ,  Masahiro Ishikawa ,  Tomohiro Sugiura

IPC分类号： B21D2200

CPC分类号： B21D53/28 ,  F16H45/02 ,  F16H2045/0284 ,  Y10T29/49471

摘要： The disclosed method produces a spline-grooved cylindrical member, e.g. torque converter front cover, including a cylindrical portion having a target wall thickness t2, from a plate blank having a plate thickness t1. An outer peripheral portion of a disc-shaped blank is plastically deformed by pressing it against a mandrel with the concave peripheral edge of a thickness-increasing roller, so that a thick wall portion, of a thickness greater than the plate thickness t1 of the blank, is formed in the cylindrical portion. The thick wall portion is then pressed against the mandrel by forming rollers to form spline grooves therein. Thus, the other portions of the product have a wall thickness which is not unnecessarily increased. In this manner, the wall thickness t2 of the cylindrical portion is not entirely dictated by the wall thickness t1 of the blank material. Thus, a cylindrical member resistant to high pressures acting on its axially-extending outer cylindrical portion can be produced with an optimal configuration.

摘要翻译： 所公开的方法产生例如花键槽的圆柱形构件。 变矩器前盖，包括具有目标壁厚度t2的圆筒部分，具有板厚t1的板坯。 通过将其压靠在具有增厚辊的凹形周缘的心轴上而使盘形坯料的外周部分发生塑性变形，使得厚度大于坯料板厚度t1的厚壁部分 形成在圆筒形部分中。 然后通过形成辊将厚壁部分压靠在心轴上，以在其中形成花键槽。 因此，产品的其它部分具有不会不必要地增加的壁厚。 以这种方式，圆筒部的壁厚t2不完全由坯料的壁厚t1决定。 因此，可以以最佳构造来制造耐受作用在其轴向延伸的外圆柱形部分上的高压的圆柱形构件。

公开(公告)号：US06869315B2

公开(公告)日：2005-03-22

申请号：US10471359

申请日：2003-04-14

申请人： Yuji Nakai ,  Koji Matsumoto

发明人： Yuji Nakai ,  Koji Matsumoto

IPC分类号： H01R24/04

CPC分类号： H01R24/58 ,  H01R12/57 ,  H01R24/40 ,  H01R2103/00 ,  H01R2107/00

摘要： In order to configure a jack (J) that realizes a favorable conductive state by bringing a tip electrode (10) at a front end of a plug (P) into reliable contact with a contact without making the jack bigger, a contact unit (CU) having a pair of tip contacts (CT) that contact the tip electrode (10) at the front end of the plug (P) in an embracing fashion is incorporated in a body (20). The contact unit (CU) is made of a linking portion (23), intermediate portions (24) that extend from both ends of the linking portion (23) towards an aperture side of the plug insertion hole (H), and folded portions (25) that are folded over from the ends of the intermediate portions (24) to the inner end side of the plug insertion hole (H), projecting into the plug insertion hole (H), the contact unit being formed in one piece by bending a band-shaped conductor, such as a copper alloy, and the tip contacts (CT) being formed on a free end side of the folded portions (25).

摘要翻译： 为了构成通过将插头（P）的前端的前端电极（10）与接点可靠地接触而不使插座变大而实现良好的导通状态的插座（J），接触单元（CU ）具有一对尖端触点（CT），其以包围的方式接触插塞（P）的前端处的尖端电极（10）并入主体（20）中。 接触单元（CU）由连接部分（23），从连接部分（23）的两端延伸到插头插入孔（H）的孔侧的中间部分（24）和折叠部分 25），其从中间部分（24）的端部折叠到插头插入孔（H）的内端侧，突出到插头插入孔（H）中，接触单元通过弯曲形成为一体 诸如铜合金的带状导体，并且尖端触头（CT）形成在折叠部分（25）的自由端侧上。

公开(公告)号：US06247034B1

公开(公告)日：2001-06-12

申请号：US09371923

申请日：1999-08-11

申请人： Yuji Nakai ,  Akihiro Furuta

发明人： Yuji Nakai ,  Akihiro Furuta

IPC分类号： G06F1714

CPC分类号： G06F17/141

摘要： In fast Fourier transform, a necessary memory capacity is decreased, thereby decreasing a cost. The fast Fourier transform is performed on a symbol stored in a RAM by a butterfly operation unit in accordance with a RAM address generated by a RAM address generator. A RAM address conversion unit converts an input/output dummy address into an input/output real address by conducting bit reverse by a frequency specified in accordance with an input/output bit reverse signal, and converts a butterfly operation dummy address into a butterfly operation real address by conducting the bit reverse by a frequency specified in accordance with a butterfly operation bit reverse signal. In this manner, among output data of one symbol and input data of another symbol to be stored in the RAM subsequently to the output data of the one symbol, data having a common index indicating their orders in the symbols can be stored at the same address in the RAM. As a result, symbol input and symbol output can be overlapped.

摘要翻译： 在快速傅里叶变换中，必要的存储容量减少，从而降低成本。 根据由RAM地址发生器产生的RAM地址，通过蝶形运算单元对存储在RAM中的符号执行快速傅立叶变换。 RAM地址转换单元通过根据输入/输出位反向信号指定的频率进行位反转而将输入/输出虚拟地址转换为输入/输出实地址，并将蝶形运算虚拟地址转换为蝶形运算实际 通过根据蝶形运算位反向信号指定的频率进行位反转。 以这种方式，在随后的一个符号的输出数据之后的一个符号的输出数据和要存储在RAM中的另一个符号的输入数据之间，具有指示它们在符号中的顺序的公共索引的数据可以存储在相同的地址 在RAM中。 结果，符号输入和符号输出可以重叠。

公开(公告)号：US08483189B2

公开(公告)日：2013-07-09

申请号：US10548377

申请日：2004-03-08

申请人： Akira Kisoda ,  Sadashi Kageyama ,  Tomohiro Kimura ,  Hiroki Furukawa ,  Kenichiro Hayashi ,  Yuji Nakai

发明人： Akira Kisoda ,  Sadashi Kageyama ,  Tomohiro Kimura ,  Hiroki Furukawa ,  Kenichiro Hayashi ,  Yuji Nakai

IPC分类号： H04B7/212 ,  H04B7/26

CPC分类号： H04W72/0446 ,  H04B7/2643 ,  H04L1/0041 ,  H04L1/0065 ,  H04L1/0071 ,  H04L5/0044 ,  H04L5/0048 ,  H04L27/2602 ,  H04L27/2647 ,  H04L27/2657 ,  H04L27/2662 ,  H04L2025/03414 ,  H04N5/4401 ,  H04N5/455 ,  H04N21/2383 ,  H04N21/41407 ,  H04N21/4382 ,  H04N21/6112

摘要： A transmission method of a digital broadcast, which is compatible with a DVB-T terrestrial digital broadcast system in Europe, saves a battery in a mobile terminal. Superframes in DVB-T are divided into units each including plural symbols so that an integer number of TS packets can be carried in each slot. At least one slot is used to transmit one service. Energy dispersion, Reed-Solomon coding, byte interleaving, convolutional coding, and time interleaving are applied to each service. When services for mobile terminal reception and services for fixed terminals are transmitted as the provided services, null packets may be transmitted before and after the slot carrying the mobile receiver service so that the fixed reception service and the mobile reception services are not mixed.

公开(公告)号：US20070274399A1

公开(公告)日：2007-11-29

申请号：US11547282

申请日：2004-11-18

申请人： Shunsuke Sakai ,  Yuji Nakai

发明人： Shunsuke Sakai ,  Yuji Nakai

IPC分类号： H04N5/14

CPC分类号： H04N5/4401 ,  H04N5/46 ,  H04N21/4305 ,  H04N21/4382 ,  H04N21/4622

摘要： A receiving apparatus (100) includes demodulation parts (101, 102) for receiving the respective one of received signals of broadast systems to output demodulated data and timing clocks synchronized with the respective demodulated data, a clock generating part (103) for outputting, to an A/V decoder (107), the two timing clocks from the demodulation parts (101, 102) as high-rate and low-rate timing clocks and for outputting a control signal for multiplexing the two demodulated data from the demodulation parts (101, 102), and a multiplexing part (104) for multiplexing, based on the control signal, the two demodulated data to output the multiplexed data to the A/V decoder (107). The A/V decoder (107) receives the multiplexed data and timing clocks from the receiving apparatus (100) to process the video/audio signals of each broadcast.

摘要翻译： 一种接收装置（100），包括用于接收广播系统的接收信号中的相应一个的解调部分（101,102），以输出与各个解调数据同步的解调数据和定时时钟;时钟发生部分（103），用于输出 A / V解码器（107），来自解调部分（101,102）的两个定时时钟作为高速和低速定时时钟，并且用于输出用于从解调部分（101）复用两个解调数据的控制信号 ，102）和多路复用部分（104），用于基于控制信号多路复用两个解调数据，以将复用的数据输出到A / V解码器（107）。 A / V解码器（107）从接收装置（100）接收多路复用数据和定时时钟，以处理每个广播的视频/音频信号。

公开(公告)号：US6115728A

公开(公告)日：2000-09-05

申请号：US010499

申请日：1998-01-21

申请人： Yuji Nakai ,  Akihiro Furuta

发明人： Yuji Nakai ,  Akihiro Furuta

IPC分类号： G06F17/14 ,  G06F15/00

CPC分类号： G06F17/141

摘要： In fast Fourier transform, a necessary memory capacity is decreased, thereby decreasing a cost. The fast Fourier transform is performed on a symbol stored in a random access memory (RAM) by a butterfly operation unit in accordance with a RAM address generated by a RAM address generator. A RAM address conversion unit converts an input/output dummy address into an input/output real address by conducting bit reverse by a frequency specified in accordance with an input/output bit reverse signal, and converts a butterfly operation dummy address into a butterfly operation real address by conducting the bit reverse by a frequency specified in accordance with a butterfly operation bit reverse signal. In this manner, among output data of one symbol and input data of another symbol to be stored in the RAM subsequently to the output data of the one symbol, data having a common index indicating their orders in the symbols can be stored at the same address in the RAM. As a result, symbol input and symbol output can be overlapped.

摘要翻译： 在快速傅里叶变换中，必要的存储容量减少，从而降低成本。 根据由RAM地址发生器产生的RAM地址，通过蝶形运算单元对存储在随机存取存储器（RAM）中的符号进行快速傅立叶变换。 RAM地址转换单元通过根据输入/输出位反向信号指定的频率进行位反转而将输入/输出虚拟地址转换为输入/输出实地址，并将蝶形运算虚拟地址转换为蝶形运算实际 通过根据蝶形运算位反向信号指定的频率进行位反转。 以这种方式，在随后的一个符号的输出数据之后的一个符号的输出数据和要存储在RAM中的另一个符号的输入数据之间，具有指示它们在符号中的顺序的公共索引的数据可以存储在相同的地址 在RAM中。 结果，符号输入和符号输出可以重叠。