公开(公告)号：US5977023A

公开(公告)日：1999-11-02

申请号：US939166

申请日：1997-09-29

申请人： Masao Inoue ,  Masao Ogawa ,  Toshiro Ohtsubo

发明人： Masao Inoue ,  Masao Ogawa ,  Toshiro Ohtsubo

IPC分类号： A01N25/10 ,  A01N25/26 ,  A01N25/12

CPC分类号： A01N25/10 ,  A01N25/26

摘要： There are discolsed a pesticidal composition containing a water-insoluble alginate, which is prepared by treating a solid composition containing (a) a pesticidally active ingredient which is a pest-controlling active ingredient or a plant growth-regulating active ingredient and (b) an alginic acid or a water-soluble alginate with an aqueous solution containing a divalent or polyvalent cation which can convert said alginic acid or water-soluble alginate into a water-insoluble alginate. Also disclosed is a pesticidal composition containing a water-insoluble alginate, which is prepared by coating a solid substance containing the pesticidally active ingredient with a water-insoluble alginate. The composition of the invention has excellent sustained-release effects of the pesticidally active ingredient.

摘要翻译： 通过处理含有（a）作为害虫控制活性成分或植物生长调节活性成分的杀虫活性成分的固体组合物和（b）含有不溶于水的藻酸盐的农药组合物， 海藻酸或水溶性藻酸盐与含有二价或多价阳离子的水溶液，其可将所述藻酸或水溶性藻酸盐转化为水不溶性藻酸盐。 还公开了含有水不溶性藻酸盐的农药组合物，其通过用含水不溶性藻酸盐包被含有杀虫活性成分的固体物质制备。 本发明的组合物具有优良的杀虫活性成分的缓释作用。

公开(公告)号：US5638402A

公开(公告)日：1997-06-10

申请号：US313384

申请日：1994-09-27

申请人： Hideki Osaka ,  Toshihiko Ogura ,  Masao Inoue

发明人： Hideki Osaka ,  Toshihiko Ogura ,  Masao Inoue

IPC分类号： G06F3/00 ,  G06F13/00 ,  H04B3/00 ,  H04L25/00

CPC分类号： H04L25/0266

摘要： A bus transceiver in a first signal processing circuit is connected to one end of a first bus connecting line for transferring a data pulse signal. A bus transceiver in a second signal processing circuit is connected to one end of a second bus connecting line for transferring a data pulse signal. Connected to the other end of the first bus connecting line is a first termination resistor. Connected to the other end of the second bus connecting line is a second termination resistor. In a portion of a predetermined length (parallel coupling portion) in the first and second bus connecting lines, the interval between the first and second bus connecting lines is held substantially constant so as to produce capacitive and inductive coupling between both the bus connecting lines. Each of the first and second bus transceivers includes a bus driver and a bus receiver. The bus receiver in the first bus transceiver generates a pulse signal substantially equal to an output pulse signal which was generated from the bus driver in the second bus transceiver, based on a pulse waveform induced in the parallel coupling portion on the first bus connecting line by the output pulse signal from the second bus transceiver.

摘要翻译： 第一信号处理电路中的总线收发器连接到用于传送数据脉冲信号的第一总线连接线的一端。 第二信号处理电路中的总线收发器连接到用于传送数据脉冲信号的第二总线连接线的一端。 连接到第一总线连接线的另一端是第一个终端电阻。 连接到第二总线连接线的另一端是第二个终端电阻。 在第一和第二总线连接线中的预定长度（平行耦合部分）的一部分中，第一和第二总线连接线之间的间隔保持基本上恒定，以便在两条总线连接线之间产生电容和电感耦合。 第一和第二总线收发器中的每一个包括总线驱动器和总线接收器。 第一总线收发器中的总线接收器基于在第一总线连接线上的并联耦合部分中感应的脉冲波形，产生基本上等于在第二总线收发器中的总线驱动器产生的输出脉冲信号的脉冲信号， 来自第二总线收发器的输出脉冲信号。

公开(公告)号：US5015524A

公开(公告)日：1991-05-14

申请号：US457242

申请日：1989-12-27

申请人： Yukio Kobayashi ,  Shoichi Nagai ,  Masatoshi Takesue ,  Fumito Aosai ,  Masao Inoue

发明人： Yukio Kobayashi ,  Shoichi Nagai ,  Masatoshi Takesue ,  Fumito Aosai ,  Masao Inoue

IPC分类号： B29C35/08 ,  B29D11/00 ,  G02B1/04 ,  G02B3/00

CPC分类号： G02B3/00 ,  B29D11/00269 ,  G02B1/041 ,  B29C2035/0827 ,  B29K2033/00 ,  Y10S428/913 ,  Y10T428/26 ,  Y10T428/31511 ,  Y10T428/31565 ,  Y10T428/31797 ,  Y10T428/31928

摘要： A lens sheet comprising a transparent substrate and a lens portion composed of a cured product of an ultraviolet-curable resin composition, which is formed on at least one surface of the transparent substrate. The resin composition exhibits a polymerization shrinkage at curing of not larger than 20% as calculated based on the difference of the specific gravity at 25.degree. C., and a modulus of elasticity at 25.degree. C. after curing of 10 to 1,000 kg/cm.sup.2. The ultraviolet-curable resin composition is preferably comprised of a polyvalent (meth)acrylate, a mono(meth)acrylate and a photopolymerization initiator.

公开(公告)号：US4729631A

公开(公告)日：1988-03-08

申请号：US43025

申请日：1987-04-27

申请人： Hideo Takahashi ,  Masao Inoue ,  Shingo Suzuki ,  Yasuaki Nakanishi

发明人： Hideo Takahashi ,  Masao Inoue ,  Shingo Suzuki ,  Yasuaki Nakanishi

IPC分类号： G03B21/62 ,  G03B21/625 ,  G03B21/60

CPC分类号： G03B21/625

摘要： Provided is a rear projection screen apparatus having a rear projection screen, light rays from a projecter being incident upon the rear surface of the rear projection screen at steep angles, wherein a plurality of elongated prisms are formed on the rear surface of the screen, each prism having a reflection surface extending therealong, thereby the incedence light rays are internally reflected, and then transmitted through the medium of screen for emerging from the front surface of the screen on the viewing side, and the rear surface of the screen is in a curve shape which is convex toward the viewing side so that the brightness of the screen can be made to be uniform.

摘要翻译： 本发明提供一种背投屏幕装置，其具有后投影屏幕，来自投影仪的光线以陡角入射在后投影屏幕的后表面上，其中多个细长棱镜形成在屏幕的后表面上，每个 棱镜具有沿其延伸的反射表面，从而内部反射入射光线，然后透过屏幕介质透过观察侧的屏幕前表面，屏幕的后表面处于曲线 形状朝向观察侧凸出，使得可以使屏幕的亮度均匀。

公开(公告)号：US07863125B2

公开(公告)日：2011-01-04

申请号：US12492648

申请日：2009-06-26

申请人： Shimpei Tsujikawa ,  Yasuhiko Akamatsu ,  Hiroshi Umeda ,  Jiro Yugami ,  Masaharu Mizutani ,  Masao Inoue ,  Junichi Tsuchimoto ,  Kouji Nomura

发明人： Shimpei Tsujikawa ,  Yasuhiko Akamatsu ,  Hiroshi Umeda ,  Jiro Yugami ,  Masaharu Mizutani ,  Masao Inoue ,  Junichi Tsuchimoto ,  Kouji Nomura

IPC分类号： H01L21/8238

CPC分类号： H01L21/823857

摘要： The manufacturing method of the CMOS type semiconductor device which can suppress the boron penetration from the gate electrode of the pMOS transistors to the semiconductor substrate in the case that boron is contained in the gate electrodes, while enabling the improvement in the NBTI lifetime of the pMOS transistors, without degrading the performance of the nMOS transistors, is offered. The manufacturing method of the CMOS type semiconductor device concerning the present invention has the following process steps. Halogen is introduced to the semiconductor substrate of pMOS transistor formation areas. Next, a gate insulating film is formed on the semiconductor substrate of the pMOS transistor formation areas. Next, nitrogen is introduced to the gate insulating film.

摘要翻译： 在这种CMOS型半导体器件的制造方法中，能够抑制在栅极电极中含有硼的情况下，从pMOS晶体管的栅电极到半导体衬底的硼渗透，同时能够提高pMOS的NBTI寿命 提供了晶体管，而不降低nMOS晶体管的性能。 关于本发明的CMOS型半导体器件的制造方法具有以下工序。 卤素引入pMOS晶体管形成区域的半导体衬底。 接下来，在pMOS晶体管形成区域的半导体衬底上形成栅极绝缘膜。 接下来，将氮引入到栅极绝缘膜。

公开(公告)号：US20100140681A1

公开(公告)日：2010-06-10

申请号：US12706659

申请日：2010-02-16

申请人： Masao Inoue

发明人： Masao Inoue

IPC分类号： H01L29/788

CPC分类号： H01L21/28211 ,  H01L21/76224 ,  H01L21/823481 ,  H01L29/40114 ,  H01L29/7881

摘要： An active region on a semiconductor substrate is electrically isolated by trench isolation. A structure of the trench isolation is constituted of a trench; a silicon oxide film formed on the inner wall of trench; an oxidation preventive film formed between silicon oxide film and semiconductor substrate; and a filling oxide film filling trench. Gate oxide film is formed by oxidation having a high capability by which radicals of at least one kind of hydrogen radicals and oxygen radicals are generated. Thereby, gate oxide film is formed so as to have a almost uniform thickness such that a thickness of a region directly above oxidation preventive film and a thickness of a region directly below gate electrode are almost the same is each other. According to the above procedure, there are obtained a semiconductor device having good transistor characteristics and a fabrication process therefor.

摘要翻译： 通过沟槽隔离将半导体衬底上的有源区电隔离。 沟槽隔离的结构由沟槽构成; 形成在沟槽内壁上的氧化硅膜; 形成在氧化硅膜和半导体衬底之间的防氧化膜; 和填充氧化物膜填充沟槽。 栅极氧化膜通过氧化而形成，其具有通过其产生至少一种氢自由基和氧自由基的自由基的高能力。 由此，栅极氧化膜形成为具有几乎均匀的厚度，使得防氧化膜正上方的区域的厚度和栅电极正下方的区域的厚度彼此相同。 根据上述步骤，获得了具有良好的晶体管特性的半导体器件及其制造工艺。

公开(公告)号：US07683455B2

公开(公告)日：2010-03-23

申请号：US11706956

申请日：2007-02-16

申请人： Masao Inoue

发明人： Masao Inoue

IPC分类号： H01L29/00

CPC分类号： H01L21/28211 ,  H01L21/28273 ,  H01L21/76224 ,  H01L21/823481 ,  H01L29/7881

摘要： An active region on a semiconductor substrate is electrically isolated by trench isolation. A structure of the trench isolation is constituted of: a trench; a silicon oxide film formed on the inner wall of trench; an oxidation preventive film formed between silicon oxide film and semiconductor substrate; and a filling oxide film filling trench. Gate oxide film is formed by oxidation having a high capability by which radicals of at least one kind of hydrogen radicals and oxygen radicals are generated. Thereby, gate oxide film is formed so as to have a almost uniform thickness such that a thickness of a region directly above oxidation preventive film and a thickness of a region directly below gate electrode are almost the same is each other. According to the above procedure, there are obtained a semiconductor device having good transistor characteristics and a fabrication process therefor.

摘要翻译： 通过沟槽隔离将半导体衬底上的有源区电隔离。 沟槽隔离的结构由沟槽构成; 形成在沟槽内壁上的氧化硅膜; 形成在氧化硅膜和半导体衬底之间的防氧化膜; 和填充氧化物膜填充沟槽。 栅极氧化膜通过氧化而形成，其具有通过其产生至少一种氢自由基和氧自由基的自由基的高能力。 由此，栅极氧化膜形成为具有几乎均匀的厚度，使得防氧化膜正上方的区域的厚度和栅电极正下方的区域的厚度彼此相同。 根据上述步骤，获得了具有良好的晶体管特性的半导体器件及其制造工艺。

公开(公告)号：US06964905B2

公开(公告)日：2005-11-15

申请号：US10095053

申请日：2002-03-12

申请人： Masao Inoue

发明人： Masao Inoue

IPC分类号： H01L21/8247 ,  H01L21/316 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/115 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L21/28211 ,  H01L21/28273 ,  H01L21/76224 ,  H01L21/823481 ,  H01L29/7881

摘要： An active region on a semiconductor substrate is electrically isolated by trench isolation. A structure of the trench isolation is constituted of: a trench; a silicon oxide film formed on the inner wall of trench; an oxidation preventive film formed between silicon oxide film and semiconductor substrate; and a filling oxide film filling trench. Gate oxide film is formed by oxidation having a high capability by which radicals of at least one kind of hydrogen radicals and oxygen radicals are generated. Thereby, gate oxide film is formed so as to have a almost uniform thickness such that a thickness of a region directly above oxidation preventive film and a thickness of a region directly below gate electrode are almost the same is each other. According to the above procedure, there are obtained a semiconductor device having good transistor characteristics and a fabrication process therefor.

摘要翻译： 通过沟槽隔离将半导体衬底上的有源区电隔离。 沟槽隔离的结构由沟槽构成; 形成在沟槽内壁上的氧化硅膜; 形成在氧化硅膜和半导体衬底之间的防氧化膜; 和填充氧化物膜填充沟槽。 栅极氧化膜通过氧化而形成，其具有通过其产生至少一种氢自由基和氧自由基的自由基的高能力。 由此，栅极氧化膜形成为具有几乎均匀的厚度，使得防氧化膜正上方的区域的厚度和栅电极正下方的区域的厚度彼此相同。 根据上述步骤，获得了具有良好的晶体管特性的半导体器件及其制造工艺。

公开(公告)号：US06683004B1

公开(公告)日：2004-01-27

申请号：US09614210

申请日：2000-07-11

申请人： Masao Inoue ,  Akinobu Teramoto ,  Hiroshi Umeda

发明人： Masao Inoue ,  Akinobu Teramoto ,  Hiroshi Umeda

IPC分类号： H01L2100

CPC分类号： H01L21/76224

摘要： There is described prevention of an increase in the thickness of an oxide film of a silicon wafer, which would otherwise be caused by eruption of gas from a CVD oxide film of another wafer during the course of a high-temperature annealing operation. A semiconductor device, which has a silicon substrate and trench isolation structures for isolating a plurality of active regions from one another, is manufactured by the steps as follows. A first and a second dielectric films are formed on the silicon substrate of one of the conductivity types. The dielectric films are removed from the areas of the silicon substrate where the trench structures are to be formed. The trench structures are formed in the uncovered areas of the silicon substrate to a predetermined depth. An oxide film is deposited into the respective trench structures by means of CVD after the oxide film has been deposited on the interior surface of the respective trench structure. The surface of the deposited oxide film is smoothed by means of removing the deposited oxide film from the silicon substrate through use of chemical-and-mechanical polishing. The second dielectric film is removed and the first dielectric film remains on the areas of the silicon substrate which are to become active regions. Then, the wafer is annealed in inactive gas at a temperature of 900° C. or less.

摘要翻译： 描述了防止硅晶片氧化膜厚度增加的原因，否则这是因为在高温退火操作过程中来自另一晶片的CVD氧化膜的气体的喷发引起的。 通过以下步骤制造具有硅衬底和用于将多个有源区彼此隔离的沟槽隔离结构的半导体器件。 在导电类型之一的硅衬底上形成第一和第二电介质膜。 从硅衬底的要形成沟槽结构的区域去除电介质膜。 沟槽结构形成在硅衬底的未覆盖区域中至预定深度。 在氧化膜沉积在相应的沟槽结构的内表面上之后，通过CVD将氧化物膜沉积到相应的沟槽结构中。 通过使用化学和机械抛光，通过从硅衬底去除沉积的氧化膜来平滑沉积的氧化物膜的表面。 去除第二电介质膜，并且第一电介质膜保留在将成为有源区的硅衬底的区域上。 然后，在900℃以下的温度下，将该晶片在惰性气体中退火。

公开(公告)号：US06662139B2

公开(公告)日：2003-12-09

申请号：US10201700

申请日：2002-07-24

申请人： Masao Inoue ,  Yasuyuki Koyagi ,  Toru Kawada ,  Toshio Tamura ,  Junichi Nagamine

发明人： Masao Inoue ,  Yasuyuki Koyagi ,  Toru Kawada ,  Toshio Tamura ,  Junichi Nagamine

IPC分类号： G06C2300

CPC分类号： B41J29/38 ,  B41J29/08

摘要： Front end clamps are disposed on the cylindrical surface of a recording drum, and rear end clamps are attached in any of a plurality of positions at the cylindrical surface of the recording drum. A controller controls a front end clamp opening/closing device to open the front end clamps and controls a pair of rollers to feed a plate held on a plate carry-in path. The controller also controls the front end clamp opening/closing device to close the plate fixing portion of the front end clamps to fix the front end of the plate on the cylindrical surface, controls a driving device to rotate the recording drum for a predetermined amount, and controls a rear end clamp attaching/detaching device to attach the rear end clamps to the cylindrical surface to fix the rear end of the plate on the recording drum cylindrical surface.

摘要翻译： 前端夹具设置在记录鼓的圆柱形表面上，并且后端夹具附着在记录鼓的圆柱形表面上的多个位置中的任一位置。 控制器控制前端夹具打开/关闭装置以打开前端夹具并且控制一对辊以进给固定在板载入路径上的板。 控制器还控制前端夹具打开/关闭装置以封闭前端夹具的板固定部分，以将板的前端固定在圆柱形表面上，控制驱动装置使记录鼓旋转预定量， 并且控制后端夹具安装/拆卸装置以将后端夹具附接到圆柱形表面，以将板的后端固定在记录鼓圆柱形表面上。