公开(公告)号：US20080013379A1

公开(公告)日：2008-01-17

申请号：US11457686

申请日：2006-07-14

申请人： Yung Feng Lin ,  Yu Shen Lin

发明人： Yung Feng Lin ,  Yu Shen Lin

IPC分类号： G11C11/34 ,  G11C16/06 ,  G11C7/02 ,  G11C7/00

CPC分类号： G11C7/12 ,  G11C7/22 ,  G11C16/24 ,  G11C16/28

摘要： Roughly described, a memory includes first and second target memory cells in a plurality of electrically adjacent memory cells all sharing a word line. The two target memory cells are separated from each other by at least one additional memory cell, and first current path terminals of the target memory cells bracket second current path terminals of the target memory cells electrically along the word line. The two target memory cells are read by connecting the first current path terminals of the two target memory cells to ground, precharging the second current path terminals of the two target memory cells to respective precharged states, and while both second current path terminals are in their respective precharged states, initiating a sense operation to read both the first and second target memory cells substantially simultaneously.

摘要翻译： 粗略地描述，存储器包括在多个电相邻的存储器单元中的共享字线的第一和第二目标存储器单元。 两个目标存储器单元由至少一个附加存储器单元彼此分离，并且目标存储器单元的第一电流路径端子沿着字线电连接目标存储器单元的第二电流路径端子。 通过将两个目标存储器单元的第一电流路径端子连接到地来读取两个目标存储器单元，将两个目标存储器单元的第二电流路径端子预充电到各自的预充电状态，并且当第二电流路径端子处于它们 相应的预充电状态，开始基本上同时读取第一和第二目标存储器单元的感测操作。

公开(公告)号：US09214859B2

公开(公告)日：2015-12-15

申请号：US13460112

申请日：2012-04-30

申请人： Yung Feng Lin ,  Chun-Jen Huang ,  Tzeng-Huei Shiau ,  Chun-Hsiung Hung ,  Caiyun Wu ,  Qifang Wang

发明人： Yung Feng Lin ,  Chun-Jen Huang ,  Tzeng-Huei Shiau ,  Chun-Hsiung Hung ,  Caiyun Wu ,  Qifang Wang

IPC分类号： H02M3/07

CPC分类号： H02M3/07

摘要： In one aspect, a first charge pump has serially arranged charge pump stages. Inter-stage nodes between adjacent stages are pumped by a second charge pump. In another aspect, timing of the charge pump stages is controlled by at a command clock signal. The command clock signal and command data are communicated between a integrated circuit with the charge pump and an external circuit.

摘要翻译： 在一个方面，第一电荷泵具有串联布置的电荷泵级。 相邻级之间的阶段节点由第二电荷泵泵送。 在另一方面，电荷泵级的定时由命令时钟信号控制。 命令时钟信号和命令数据在与电荷泵的集成电路和外部电路之间传送。

公开(公告)号：US08264274B2

公开(公告)日：2012-09-11

申请号：US13301534

申请日：2011-11-21

申请人： Yung Feng Lin ,  Nai-Ping Kuo

发明人： Yung Feng Lin ,  Nai-Ping Kuo

IPC分类号： G05F1/10

CPC分类号： H02M3/073 ,  G11C5/145 ,  H02M2001/0032 ,  H02M2003/075 ,  Y02B70/16

摘要： A charge pump apparatus comprises a plurality of charge pump stages. The charge pump stages each include a respective output node. Output nodes are connected to charge boosting circuitry and to precharge circuitry. The charge boosting circuit receives one or more clock signals. The precharge circuits have a first state allowing the respective pump-stage output node to fluctuate at a level above a standby wordline voltage, and a second state coupling the respective pump-stage output node to the standby wordline voltage.

摘要翻译： 电荷泵装置包括多个电荷泵级。 电荷泵级各自包括相应的输出节点。 输出节点连接到充电升压电路和预充电电路。 充电提升电路接收一个或多个时钟信号。 预充电电路具有允许相应的泵级输出节点在待机字线电压以上的水平波动的第一状态，以及将相应的泵级输出节点耦合到备用字线电压的第二状态。

公开(公告)号：US08077528B2

公开(公告)日：2011-12-13

申请号：US12715504

申请日：2010-03-02

申请人： Jer-Hau Hsu ,  Yung Feng Lin

发明人： Jer-Hau Hsu ,  Yung Feng Lin

IPC分类号： G11C5/14

CPC分类号： G11C7/12

摘要： A bit-line voltage generator is provided. The bit-line voltage generator includes a discharge enhanced bias source and a switch unit. The switch unit includes a clamp transistor having a source, a gate connected to the discharge enhanced bias source, and a drain receiving a voltage; a switch transistor having a gate receiving a control signal, a drain connected to the source of the clamp transistor, and a source connected to a memory array, wherein a parasitic capacitor exists between the gate and the source of the clamp transistor; a resistor having a first terminal connected to the drain of the switch transistor, and a second terminal connected to ground; and a capacitor having a first terminal connected to the drain of the switch transistor, and a second terminal connected to ground, wherein a charge in the parasitic capacitor, when the switch transistor is turned on, is almost identical to that when the switch transistor is turned off, so that a couple effect between the switch unit and the discharge enhanced bias source is reduced, thereby stabilizing a bias applied to the memory array.

摘要翻译： 提供了位线电压发生器。 位线电压发生器包括放电增强偏置源和开关单元。 开关单元包括具有源极，连接到放电增强偏置源的栅极和接收电压的漏极的钳位晶体管; 具有接收控制信号的栅极的开关晶体管，连接到钳位晶体管的源极的漏极和连接到存储器阵列的源极，其中寄生电容器存在于钳位晶体管的栅极和源极之间; 电阻器，其具有连接到开关晶体管的漏极的第一端子和连接到地的第二端子; 以及电容器，其具有连接到开关晶体管的漏极的第一端子和连接到地的第二端子，其中当开关晶体管导通时，寄生电容器中的电荷几乎与开关晶体管为 关闭，使得开关单元和放电增强偏置源之间的耦合效应降低，从而稳定施加到存储器阵列的偏置。

公开(公告)号：US20090195270A1

公开(公告)日：2009-08-06

申请号：US12024404

申请日：2008-02-01

申请人： Yung Feng Lin

发明人： Yung Feng Lin

IPC分类号： H03K19/0175

CPC分类号： H03K19/00361 ,  G11C7/02 ,  G11C7/04 ,  G11C7/1051 ,  G11C7/1057 ,  H03K19/0013 ,  H03K19/00384

摘要： A controlling output buffer slew rate method and an output buffer circuit for a memory device is provided. The output buffer include an output stage formed by a PMOS transistor and a NMOS transistor electrically connected in series, a pre-driver for respectively controlling each gate terminal of the PMOS transistor and the NMOS transistor in order to bring these transistors to the turning-on threshold, a first wire, for transmitting a pull-up signal, coupled between the output stage and the pre-driver, and a second wire, for transmitting a pull-down signal, coupled between the output stage and the pre-driver. After a DATA signal transition (logic state is changed from “H” to “L” or “L” from to “H”), the PMOS or NMOS transistor is turned off first, and then the NMOS or PMOS transistor is turned on due to the time difference between the pull-up signal and the pull-down signal.

摘要翻译： 提供了控制输出缓冲器转换速率方法和用于存储器件的输出缓冲器电路。 输出缓冲器包括由PMOS晶体管和串联电连接的NMOS晶体管形成的输出级，用于分别控制PMOS晶体管和NMOS晶体管的每个栅极端子的预驱动器，以便使这些晶体管导通 阈值，用于传输耦合在输出级和预驱动器之间的上拉信号的第一引线和用于传输耦合在输出级和预驱动器之间的下拉信号的第二引线。 在DATA信号转换（逻辑状态从“H”变为“L”或“L”从“H”）开始，PMOS或NMOS晶体管首先关断，然后NMOS或PMOS晶体管导通， 到上拉信号和下拉信号之间的时间差。

公开(公告)号：US20090168554A1

公开(公告)日：2009-07-02

申请号：US11967677

申请日：2007-12-31

申请人： Jer-Hau Hsu ,  Yung Feng Lin

发明人： Jer-Hau Hsu ,  Yung Feng Lin

IPC分类号： G11C7/12

CPC分类号： G11C7/12

摘要： A bit-line voltage generator is provided. The bit-line voltage generator includes a discharge enhanced bias source and a switch unit. The switch unit includes a clamp transistor having a source, a gate connected to the discharge enhanced bias source, and a drain receiving a voltage; a switch transistor having a gate receiving a control signal, a drain connected to the source of the clamp transistor, and a source connected to a memory array, wherein a parasitic capacitor exists between the gate and the source of the clamp transistor; a resistor having a first terminal connected to the drain of the switch transistor, and a second terminal connected to ground; and a capacitor having a first terminal connected to the drain of the switch transistor, and a second terminal connected to ground, wherein a charge in the parasitic capacitor, when the switch transistor is turned on, is almost identical to that when the switch transistor is turned off, so that a couple effect between the switch unit and the discharge enhanced bias source is reduced, thereby stabilizing a bias applied to the memory array.

摘要翻译： 提供了位线电压发生器。 位线电压发生器包括放电增强偏置源和开关单元。 开关单元包括具有源极，连接到放电增强偏置源的栅极和接收电压的漏极的钳位晶体管; 具有接收控制信号的栅极的开关晶体管，连接到钳位晶体管的源极的漏极和连接到存储器阵列的源极，其中寄生电容器存在于钳位晶体管的栅极和源极之间; 电阻器，其具有连接到开关晶体管的漏极的第一端子和连接到地的第二端子; 以及电容器，其具有连接到开关晶体管的漏极的第一端子和连接到地的第二端子，其中当开关晶体管导通时，寄生电容器中的电荷几乎与开关晶体管为 关闭，使得开关单元和放电增强偏置源之间的耦合效应降低，由此稳定施加到存储器阵列的偏置。

公开(公告)号：US07463539B2

公开(公告)日：2008-12-09

申请号：US11619062

申请日：2007-01-02

申请人： Yung Feng Lin

发明人： Yung Feng Lin

IPC分类号： G11C7/00

CPC分类号： G11C7/12 ,  G11C7/1018 ,  G11C7/1048 ,  G11C11/4094 ,  G11C11/4096

摘要： A memory device operates according to a method for reading includes pre-charging a first set of selected bit lines to a pre-charge voltage and sensing data from the cells coupled to the first set of selected bit lines. Then, residual charge is transferred from the first set of selected bit lines to corresponding members of a second set of selected bit lines. The second set of selected bit lines, having an initial charge transferred from the first set, is then pre-charged to the pre-charge voltage. The data from the cells coupled to the second set of selected bit lines it is then sensed. In embodiments described herein, the read operation occurs in a burst read mode, where a volume of data having consecutive addresses is read.

摘要翻译： 存储器件根据用于读取的方法进行操作，包括将第一组选定位线预先充电到预充电电压，并感测来自耦合到第一组选定位线的单元的数据。 然后，剩余电荷从第一组选定位线传送到第二组选定位线的相应部件。 然后将具有从第一组转移的初始电荷的第二组选定位线预充电到预充电电压。 然后感测来自耦合到第二组选定位线的单元的数据。 在本文描述的实施例中，读操作以突发读取模式发生，其中读取具有连续地址的数据量。

公开(公告)号：US20130285737A1

公开(公告)日：2013-10-31

申请号：US13460112

申请日：2012-04-30

申请人： Yung Feng Lin ,  Chun-Jen Huang ,  Tzeng-Huei Shiau ,  Chun-Hsiung Hung ,  Caiyun Wu ,  Qifang Wang

发明人： Yung Feng Lin ,  Chun-Jen Huang ,  Tzeng-Huei Shiau ,  Chun-Hsiung Hung ,  Caiyun Wu ,  Qifang Wang

IPC分类号： G05F3/02

CPC分类号： H02M3/07

摘要： In one aspect, a first charge pump has serially arranged charge pump stages. Inter-stage nodes between adjacent stages are pumped by a second charge pump. In another aspect, timing of the charge pump stages is controlled by at a command clock signal. The command clock signal and command data are communicated between a integrated circuit with the charge pump and an external circuit.

摘要翻译： 在一个方面，第一电荷泵具有串联布置的电荷泵级。 相邻级之间的阶段节点由第二电荷泵泵送。 在另一方面，电荷泵级的定时由命令时钟信号控制。 命令时钟信号和命令数据在与电荷泵的集成电路和外部电路之间传送。

公开(公告)号：US20120269009A1

公开(公告)日：2012-10-25

申请号：US13089835

申请日：2011-04-19

申请人： Yung Feng Lin

发明人： Yung Feng Lin

IPC分类号： G11C7/12

CPC分类号： G11C7/12 ,  G11C16/24 ,  G11C16/28

摘要： An integrated circuit includes an array of memory cells with a plurality of columns and rows. A plurality of data lines is coupled to the columns in the array and a plurality of word lines is coupled to the rows in the array. Clamp transistors are coupled to respective data lines in the plurality of data lines, and adapted to prevent voltage on the respective bit lines from overshooting a target level during a precharge interval. A bias circuit is coupled to the clamp transistors on the plurality of bit lines, and arranged to apply the bias voltage in at least two phases within a precharge interval, and to prevent overshoot of the target level on the bit line.

摘要翻译： 集成电路包括具有多个列和行的存储器单元的阵列。 多个数据线耦合到阵列中的列，并且多个字线耦合到阵列中的行。 钳位晶体管耦合到多条数据线中的相应数据线，并且适于防止相应位线上的电压在预充电间隔期间过冲目标电平。 偏置电路耦合到多个位线上的钳位晶体管，并且被布置为在预充电间隔内以至少两个相位施加偏置电压，并且防止位线上的目标电平的过冲。

公开(公告)号：US08085086B1

公开(公告)日：2011-12-27

申请号：US12839663

申请日：2010-07-20

申请人： Yung Feng Lin ,  Nai-Ping Kuo

发明人： Yung Feng Lin ,  Nai-Ping Kuo

IPC分类号： G05F1/10

CPC分类号： H02M3/073 ,  G11C5/145 ,  H02M2001/0032 ,  H02M2003/075 ,  Y02B70/16

摘要： A charge pump apparatus comprises a plurality of charge pump stages, including a first stage, and one or more succeeding stages. The charge pump stages each include a respective output node. Each output node is connected to charge boosting circuitry and to precharge circuitry. The charge boosting circuit receives one or more clock signals. The precharge circuits have a first state allowing the respective pump-stage output node to fluctuate at a level above a standby wordline voltage, and a second state coupling the respective pump-stage output node to the standby wordline voltage.

摘要翻译： 电荷泵装置包括多个电荷泵级，包括第一级和一个或多个后续级。 电荷泵级各自包括相应的输出节点。 每个输出节点连接到充电升压电路和预充电电路。 充电提升电路接收一个或多个时钟信号。 预充电电路具有允许相应的泵级输出节点在待机字线电压以上的水平波动的第一状态，以及将相应的泵级输出节点耦合到备用字线电压的第二状态。