公开(公告)号：US06630864B2

公开(公告)日：2003-10-07

申请号：US10341020

申请日：2003-01-13

申请人： Jungwook Yang

发明人： Jungwook Yang

IPC分类号： H03F345

CPC分类号： H03F3/45089 ,  H03F3/45098 ,  H03F3/45502 ,  H03F2203/45646 ,  H03F2203/45702

摘要： A system and method of controlling the operation of linear variable-gain amplifiers to allow for such linear variable gain amplifiers to have a wider operating range at high current levels, control inputs for selectable gains and improved low-voltage operation. In a first mode, the amplifier includes an additional source of current to allow for an enhanced operating range. In a second embodiment, the amplifier includes a plurality of selective resistive levels and a selection system which allows the selection of one of the resistive levels which, in turn, controls the gain range of the amplifier system of the present invention. A third embodiment of the present invention illustrates the use of an amplifier system useful for a low voltage input signal to reduce errors caused by variations in the base to emitter in the two transistors providing the amplification. Also disclosed are embodiments for reducing the error in the amplifier output by providing additional stages to provide error reducing components which are added to the amplifier output.

公开(公告)号：US06563382B1

公开(公告)日：2003-05-13

申请号：US09685813

申请日：2000-10-10

申请人： Jungwook Yang

发明人： Jungwook Yang

IPC分类号： H03F345

CPC分类号： H03F3/45089 ,  H03F3/45098 ,  H03F3/45502 ,  H03F2203/45646 ,  H03F2203/45702

摘要： A system and method of controlling the operation of linear variable-gain amplifiers to allow for such linear variable gain amplifiers to have a wider operating range at high current levels, control inputs for selectable gains and improved low-voltage operation. In a first mode, the amplifier includes an additional source of current to allow for an enhanced operating range. In a second embodiment, the amplifier includes a plurality of selective resistive levels and a selection system which allows the selection of one of the resistive levels which, in turn, controls the gain range of the amplifier system of the present invention. A third embodiment of the present invention illustrates the use of an amplifier system useful for a low voltage input signal to reduce errors caused by variations in the base to emitter in the two transistors providing the amplification. Also disclosed are embodiments for reducing the error in the amplifier output by providing additional stages to provide error reducing components which are added to the amplifier output.

摘要翻译： 控制线性可变增益放大器的操作的系统和方法，以允许这种线性可变增益放大器在高电流水平下具有更宽的工作范围，控制输入以获得可选择的增益和改进的低电压操作。 在第一模式中，放大器包括额外的电流源以允许增强的操作范围。 在第二实施例中，放大器包括多个选择性电阻电平和选择系统，其允许选择电阻电平中的一个，这进而控制本发明的放大器系统的增益范围。 本发明的第三实施例示出了对于低电压输入信号有用的放大器系统的用途，以减少由提供放大的两个晶体管中的基极到发射极的变化引起的误差。 还公开了用于通过提供附加级来提供放大器输出中的误差减小部件来减小放大器输出中的误差的实施例。

公开(公告)号：US06429691B1

公开(公告)日：2002-08-06

申请号：US09751508

申请日：2000-12-29

申请人： Jungwook Yang

发明人： Jungwook Yang

IPC分类号： H03K1920

CPC分类号： H03K19/017527

摘要： A circuit provides differential logic signals and includes a differential-input circuit having a first differential input and a second differential input. A first unit receives an input voltage signal and a supply voltage for providing a first voltage to the first differential input via a first node. A second unit receives the supply voltage for providing a second voltage to the second differential input via a second node. The differential-input circuit outputs a signal in accordance with the first and second voltages.

摘要翻译： 电路提供差分逻辑信号，并且包括具有第一差分输入和第二差分输入的差分输入电路。 第一单元接收输入电压信号和用于经由第一节点向第一差分输入提供第一电压的电源电压。 第二单元接收用于经由第二节点向第二差分输入提供第二电压的电源电压。 差分输入电路根据第一和第二电压输出信号。

公开(公告)号：US06518797B2

公开(公告)日：2003-02-11

申请号：US09753268

申请日：2000-12-29

申请人： Jungwook Yang

发明人： Jungwook Yang

IPC分类号： H03K19086

CPC分类号： H03K19/01837 ,  H03K19/0826 ,  H03K19/086

摘要： In a current mode logic (CML) circuit, a high impedance state is implemented at the output for a bi-directional buffer. The output common mode voltage can be adjusted at the same time, which is particularly useful for a CML off-chip driver.

摘要翻译： 在电流模式逻辑（CML）电路中，在双向缓冲器的输出端实现高阻抗状态。 可以同时调节输出共模电压，这对于CML片外驱动器特别有用。

公开(公告)号：US20210028792A1

公开(公告)日：2021-01-28

申请号：US16937553

申请日：2020-07-23

申请人： Sewook Hwang ,  Jungwook Yang ,  Kailiang Chen ,  Nevada J. Sanchez ,  Keith G. Fife

发明人： Sewook Hwang ,  Jungwook Yang ,  Kailiang Chen ,  Nevada J. Sanchez ,  Keith G. Fife

IPC分类号： H03M1/12 ,  A61B8/00

摘要： Aspects of the technology described herein relate to control circuitry configured to turn on and off the ADC driver. In some embodiments, the control circuitry is configured to turn on and off the ADC driver in synchronization with sampling activity of an ADC, in particular based on when an ADC is sampling. The control circuitry may be configured to turn on the ADC driver during the hold phase of the ADC a time period before the track phase and to turn off the ADC driver during the hold phase a time period after the track phase. In some embodiments, the control circuitry is configured to control a duty cycle of the ADC driver turning on and off. In some embodiments, the control circuitry is configured to control a ratio between an off current and an on current in the ADC driver.

公开(公告)号：US20190336099A1

公开(公告)日：2019-11-07

申请号：US16401870

申请日：2019-05-02

申请人： Keith G. Fife ,  Jianwei Liu ,  Jungwook Yang ,  Joseph Lutsky

发明人： Keith G. Fife ,  Jianwei Liu ,  Jungwook Yang ,  Joseph Lutsky

IPC分类号： A61B8/12 ,  B06B1/02 ,  G01N29/24 ,  B06B1/06 ,  H01L41/09

摘要： Micromachined ultrasonic transducers having pressure ports are described. The micromachined ultrasonic transducers may comprise flexible membranes configured to vibrate over a cavity. The cavity may be sealed, in some instances by the membrane itself. A pressure port may provide access to the cavity, and thus control of the cavity pressure. In some embodiments, an ultrasound device including an array of micromachined ultrasonic transducers is provided, with pressure ports for at least some of the ultrasonic transducers. The pressure ports may be used to control pressure across the array.

公开(公告)号：US07446805B2

公开(公告)日：2008-11-04

申请号：US10752131

申请日：2004-01-06

申请人： Hae-Seung Lee ,  Keith Glen Fife ,  Lane G. Brooks ,  Jungwook Yang

发明人： Hae-Seung Lee ,  Keith Glen Fife ,  Lane G. Brooks ,  Jungwook Yang

IPC分类号： H04N5/217

CPC分类号： H04N5/3597 ,  H04N5/363 ,  H04N5/3698 ,  H04N5/374 ,  H04N5/3745

摘要： A circuit for a pixel site in an imaging array includes a light-detecting element to convert incident light to a photocurrent and a reset transistor, operatively connected to the light-detecting element, to reset a voltage associated with the light-detecting element. The reset transistor hard resets the voltage associated with the light-detecting element and soft resets the voltage associated with the light-detecting element after the generation of the hard reset of the voltage associated with the light-detecting element. A pixel voltage of a column or row line is also measured by hard resetting the column or row line voltage to a first predetermined voltage; soft resetting the column or row line voltage to a first pixel voltage; hard resetting the column or row line voltage to a second predetermined voltage; soft resetting the column or row line voltage to a second pixel voltage; and determining a difference between the first and second pixel voltages, the difference being the measured pixel voltage.

摘要翻译： 用于成像阵列中的像素位置的电路​​包括将入射光转换为光电流的光检测元件和可操作地连接到光检测元件的复位晶体管，以复位与光检测元件相关联的电压。 复位晶体管硬复位与光检测元件相关联的电压，并且在与光检测元件相关联的电压的硬复位产生之后，软复位与光检测元件相关联的电压。 通过将列或行线电压硬复位到第一预定电压也测量列或行线的像素电压; 将列或行线电压软复位为第一像素电压; 将列或行线电压硬复位到第二预定电压; 将列或行线电压软复位到第二像素电压; 以及确定所述第一和第二像素电压之间的差，所述差是所测量的像素电压。

公开(公告)号：US06570522B1

公开(公告)日：2003-05-27

申请号：US10042190

申请日：2002-01-11

申请人： Tibi Galambos ,  Viktor Ariel ,  Jungwook Yang ,  Eliyahu Shamsaev

发明人： Tibi Galambos ,  Viktor Ariel ,  Jungwook Yang ,  Eliyahu Shamsaev

IPC分类号： H03M112

CPC分类号： H03M1/205 ,  H03M1/141

摘要： An analog-to-digital converter (ADC), including a plurality of first-level folded-differential-logic-encoders (FDLEs), coupled to receive an analog input signal and respective reference voltages and to provide respective outputs responsive to comparing a magnitude of the input signal to the respective reference voltages. The ADC has a second-level resultant FDLE, which is coupled to receive and combine the outputs of the first-level FDLEs to provide a digital value indicative of the magnitude of the input signal.

摘要翻译： 一种模数转换器（ADC），包括多个第一级折叠 - 差分逻辑编码器（FDLE），其被耦合以接收模拟输入信号和相应参考电压，并且响应于比较幅度 的输入信号。 ADC具有第二级结合FDLE，其被耦合以接收和组合第一级FDLE的输出，以提供指示输入信号的幅度的数字值。

公开(公告)号：US20190336104A1

公开(公告)日：2019-11-07

申请号：US16401630

申请日：2019-05-02

申请人： KEITH G. FIFE ,  Jianwei Liu ,  Joseph Lutsky ,  Sarp Satir ,  Jungwook Yang

发明人： KEITH G. FIFE ,  Jianwei Liu ,  Joseph Lutsky ,  Sarp Satir ,  Jungwook Yang

IPC分类号： A61B8/00 ,  A61B8/06

摘要： An ultrasound device is described. The ultrasound device may include a cavity, a membrane, and a sensing electrode. When an electrical signal is applied to the sensing electrode and a static bias is applied to the membrane, the membrane vibrates within the cavity and produces ultrasonic signals. The cavity, the membrane, and the sensing electrode may be considered a capacitive micromachined ultrasonic transducer (CMUT). The sensing electrode may be shaped as a ring, whereby the central portion of the sensing electrode is removed. Removal of the central portion of the sensing electrode may reduce the parasitic capacitance without substantially affecting the production of ultrasonic signals by the CMUT. This, in turn, can result in an increase in the signal-to-noise ratio (SNR) of the ultrasonic signals. The ultrasound device may further include a bond pad configured for wire bonding, and a trench electrically isolating the bond pad from the membrane.

公开(公告)号：US20080224743A1

公开(公告)日：2008-09-18

申请号：US11856301

申请日：2007-09-17

申请人： Jungwook Yang ,  Lane Brooks ,  Pavan Mudunuru

发明人： Jungwook Yang ,  Lane Brooks ,  Pavan Mudunuru

IPC分类号： H03L7/00

CPC分类号： H03K5/135

摘要： A circuit for generating non-overlapping clock signals includes a programmable delayed reference clock signals circuit to produce a plurality of delayed reference clock signals and a plurality of delay clock signal generators, operatively connected to the programmable delayed reference clock signals circuit, to generate non-overlapping clock signals. Each delay clock signal generator includes a latch or flip-flop to control a delay in a rising edge of a clock signal and to output a first signal, another latch or flip-flop to control a delay in a falling edge of a delayed clock signal and to output a first signal, and a logic circuit to generate the clock signal from the first and second signals. The latches or flip-flops independently control a delay in the rising edge of the clock signal in response to one of the plurality of delayed reference clock signals.

摘要翻译： 用于产生非重叠时钟信号的电路包括可编程延迟参考时钟信号电路以产生多个延迟参考时钟信号，以及多个延迟时钟信号发生器，可操作地连接到可编程延迟参考时钟信号电路， 重叠时钟信号。 每个延迟时钟信号发生器包括锁存器或触发器，以控制时钟信号的上升沿的延迟并输出第一信号，另一个锁存器或触发器来控制延迟的时钟信号的下降沿中的延迟 并且输出第一信号，以及逻辑电路，以从第一和第二信号产生时钟信号。 锁存器或触发器响应于多个延迟的参考时钟信号中的一个独立地控制时钟信号的上升沿中的延迟。