公开(公告)号：US20130036332A1

公开(公告)日：2013-02-07

申请号：US13198904

申请日：2011-08-05

申请人： Darryl J. Gove ,  Zoran Radovic ,  Jonathan Adams

发明人： Darryl J. Gove ,  Zoran Radovic ,  Jonathan Adams

IPC分类号： G06F11/14

CPC分类号： G06F21/52 ,  G06F11/0724 ,  G06F11/0763

摘要： Systems and methods for maximizing a number of available states for a version number used for memory corruption detection. A physical memory may be a DRAM comprising a plurality of regions. Version numbers associated with data structures allocated in the physical memory may be generated so that version numbers of adjacent data structures in a virtual address space are different. A reserved set and an available set of version numbers are associated with each one of the plurality of regions. A version number in a reserved set of a given region may be in an available set of another region. The processor detects no memory corruption error in response to at least determining a version number stored in a memory location in a first region identified by a memory access operation is also in a reserved set associated with the first region.

摘要翻译： 用于最大化用于内存损坏检测的版本号的可用状态数量的系统和方法。 物理存储器可以是包括多个区域的DRAM。 可以生成与物理存储器中分配的数据结构相关联的版本号，使得虚拟地址空间中的相邻数据结构的版本号不同。 保留集合和可用的版本号集合与多个区域中的每一个相关联。 给定区域的保留集合中的版本号可以在另一区域的可用集合中。 响应于至少确定存储在由存储器访问操作识别的第一区域中的存储器位置中的版本号也处于与第一区域相关联的保留集中，处理器不检测存储器损坏错误。

公开(公告)号：US07412567B2

公开(公告)日：2008-08-12

申请号：US11413243

申请日：2006-04-28

申请人： Håkan E. Zeffer ,  Erik E. Hagersten ,  Anders Landin ,  Shailender Chaudhry ,  Paul N. Loewenstein ,  Robert E. Cypher ,  Zoran Radovic

发明人： Håkan E. Zeffer ,  Erik E. Hagersten ,  Anders Landin ,  Shailender Chaudhry ,  Paul N. Loewenstein ,  Robert E. Cypher ,  Zoran Radovic

IPC分类号： G06F12/00

CPC分类号： G06F12/0815 ,  G06F12/0808 ,  G06F12/0822 ,  G06F12/0897

摘要： In one embodiment, a processor comprises a coherence trap unit and a trap logic coupled to the coherence trap unit. The coherence trap unit is also coupled to receive data accessed in response to the processor executing a memory operation. The coherence trap unit is configured to detect that the data matches a designated value indicating that a coherence trap is to be initiated to coherently perform the memory operation. The trap logic is configured to trap to a designated software routine responsive to the coherence trap unit detecting the designated value. In some embodiments, a cache tag in a cache may track whether or not the corresponding cache line has the designated value, and the cache tag may be used to trigger a trap in response to an access to the corresponding cache line.

摘要翻译： 在一个实施例中，处理器包括相干陷阱单元和耦合到相干陷波单元的陷波逻辑。 相干陷阱单元还被耦合以接收响应于处理器执行存储器操作而访问的数据。 相干陷阱单元被配置为检测数据与指示要发起的相干陷阱的指定值匹配以相干地执行存储器操作。 陷阱逻辑被配置为响应于相干陷阱单元检测到指定值而陷入指定的软件例行程序。 在一些实施例中，高速缓存中的高速缓存标签可以跟踪对应的高速缓存行是否具有指定值，并且可以使用高速缓存标签来响应对对应的高速缓存行的访问来触发陷阱。

公开(公告)号：US08806145B2

公开(公告)日：2014-08-12

申请号：US12266719

申请日：2008-11-07

申请人： Zoran Radovic ,  Erik Martin Roland Karlsson

发明人： Zoran Radovic ,  Erik Martin Roland Karlsson

IPC分类号： G06F12/00

CPC分类号： G06F12/0862

摘要： Methods and apparatuses are disclosed for improving speculation success in processors. In some embodiments, the method may include executing a plurality of threads of program code, the plurality of threads comprising a first speculative load request, setting an indicator bit corresponding to a cache line in response to the first speculative load request, and in the event that a second speculative load request from the plurality of threads refers to a first cache line with the indicator bit set, determining if a second cache line is available.

摘要翻译： 公开了用于改善处理器中的投机成功的方法和装置。 在一些实施例中，该方法可以包括执行程序代码的多个线程，所述多个线程包括第一推测加载请求，响应于第一推测加载请求设置对应于高速缓存行的指示符位，并且在该事件中 来自多个线程的第二推测加载请求是指具有指示符位置位的第一高速缓存行，确定第二高速缓存行是否可用。

公开(公告)号：US08788766B2

公开(公告)日：2014-07-22

申请号：US12708376

申请日：2010-02-18

申请人： John R. Rose ,  Lawrence A. Spracklen ,  Zoran Radovic

发明人： John R. Rose ,  Lawrence A. Spracklen ,  Zoran Radovic

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F9/30021 ,  G06F9/30018

摘要： A method and processor supporting architected instructions for tracking and determining set membership, such as by implementing Bloom filters are disclosed. The apparatus includes storage arrays (e.g., registers) and an execution core configured to store an indication that a given value is a member of a set, including by executing an architected instruction having an operand specifying the given value, wherein executing comprises applying a hash function to the value to determine an index into one of the storage arrays and setting a bit of the storage array corresponding to the index. An architected query instruction is later executed to determine if a query value is not a member of the set, including by applying the hash function to the query value to determine an index into the storage array and determining whether a bit at the index of the storage array is set.

摘要翻译： 公开了一种支持用于跟踪和确定集合成员资格的架构指令的方法和处理器，例如通过实现Bloom过滤器。 该装置包括存储阵列（例如，寄存器）和被配置为存储给定值是组的成员的指示的执行核心，包括通过执行具有指定给定值的操作数的架构化指令，其中执行包括应用散列 函数到该值以确定一个索引到一个存储阵列中并设置与该索引对应的存储阵列的位。 稍后执行架构化查询指令以确定查询值是否不是该集合的成员，包括通过将哈希函数应用于查询值来确定存储阵列中的索引并确定存储器的索引处的位 数组被设置。

公开(公告)号：US07529844B2

公开(公告)日：2009-05-05

申请号：US10422454

申请日：2003-04-24

申请人： Zoran Radovic ,  Erik E. Hagersten

发明人： Zoran Radovic ,  Erik E. Hagersten

IPC分类号： G06F15/16

CPC分类号： G06F9/526

摘要： A method for controlling a software lock acquirable by processors in a plurality of nodes of a multiprocessing system is disclosed. The method comprises a first processor of a first node of the plurality of nodes acquiring the lock, and the first processor selectively releasing the lock in a first state that allows other processors within the first node to acquire the lock but that prevents processors in a remote node of the plurality of nodes from obtaining the lock. In another embodiment, a method comprises a first processor of a first node attempting to acquire the lock, the first processor determining whether another processor within the same node is remotely spinning on the lock, and the first processor remotely spinning on the lock in response to determining that another processor in the same node is not remotely spinning on the software lock.

摘要翻译： 公开了一种用于控制由多处理系统的多个节点中的处理器获取的软件锁定的方法。 该方法包括：多个节点中的第一节点的第一处理器获取锁定，并且第一处理器选择性地释放锁，该第一状态允许第一节点内的其他处理器获取锁定，但是防止处于远程 多个节点的节点获得锁定。 在另一个实施例中，一种方法包括尝试获取锁的第一节点的第一处理器，第一处理器确定同一节点内的另一个处理器是否在锁上进行远程旋转，并且第一处理器响应于 确定同一节点中的另一个处理器不会在软件锁上远程旋转。

公开(公告)号：US08572441B2

公开(公告)日：2013-10-29

申请号：US13198904

申请日：2011-08-05

申请人： Darryl J. Gove ,  Zoran Radovic ,  Jonathan Adams

发明人： Darryl J. Gove ,  Zoran Radovic ,  Jonathan Adams

IPC分类号： G06F11/00 ,  G06F11/10

CPC分类号： G06F21/52 ,  G06F11/0724 ,  G06F11/0763

摘要： Systems and methods for maximizing a number of available states for a version number used for memory corruption detection. A physical memory may be a DRAM comprising a plurality of regions. Version numbers associated with data structures allocated in the physical memory may be generated so that version numbers of adjacent data structures in a virtual address space are different. A reserved set and an available set of version numbers are associated with each one of the plurality of regions. A version number in a reserved set of a given region may be in an available set of another region. The processor detects no memory corruption error in response to at least determining a version number stored in a memory location in a first region identified by a memory access operation is also in a reserved set associated with the first region.

摘要翻译： 用于最大化用于内存损坏检测的版本号的可用状态数量的系统和方法。 物理存储器可以是包括多个区域的DRAM。 可以生成与物理存储器中分配的数据结构相关联的版本号，使得虚拟地址空间中的相邻数据结构的版本号不同。 保留集合和可用的版本号集合与多个区域中的每一个相关联。 给定区域的保留集合中的版本号可以在另一区域的可用集合中。 响应于至少确定存储在由存储器访问操作识别的第一区域中的存储器位置中的版本号也处于与第一区域相关联的保留集中，处理器不检测存储器损坏错误。

公开(公告)号：US20100122036A1

公开(公告)日：2010-05-13

申请号：US12266719

申请日：2008-11-07

申请人： Zoran Radovic ,  Erik Martin Roland Karlsson

发明人： Zoran Radovic ,  Erik Martin Roland Karlsson

IPC分类号： G06F12/08

CPC分类号： G06F12/0862

摘要： Methods and apparatuses are disclosed for improving speculation success in processors. In some embodiments, the method may include executing a plurality of threads of program code, the plurality of threads comprising a first speculative load request, setting an indicator bit corresponding to a cache line in response to the first speculative load request, and in the event that a second speculative load request from the plurality of threads refers to a first cache line with the indicator bit set, determining if a second cache line is available.

摘要翻译： 公开了用于改善处理器中的投机成功的方法和装置。 在一些实施例中，该方法可以包括执行程序代码的多个线程，所述多个线程包括第一推测加载请求，响应于第一推测加载请求设置对应于高速缓存行的指示符位，并且在该事件中 来自多个线程的第二推测加载请求是指具有指示符位置位的第一高速缓存行，确定第二高速缓存行是否可用。