公开(公告)号：US07509460B2

公开(公告)日：2009-03-24

申请号：US11417640

申请日：2006-05-04

申请人： Håkan E. Zeffer ,  Anders Landin ,  Erik E. Hagersten

发明人： Håkan E. Zeffer ,  Anders Landin ,  Erik E. Hagersten

IPC分类号： G06F12/00 ,  G06F13/00

CPC分类号： G06F12/0815

摘要： In one embodiment, a memory controller for a node in a multi-node computer system comprises logic and a control unit. The logic is configured to determine if an address corresponding to a request received by the memory controller on an intranode interconnect is a remote address or a local address. A first portion of the memory in the node is allocated to store copies of remote data and a remaining portion stores local data. The control unit is configured to write writeback data to a location in the first portion. The writeback data corresponds to a writeback request from the intranode interconnect that has an associated remote address detected by the logic. The control unit is configured to determine the location responsive to the associated remote address and one or more indicators that identify the first portion in the memory.

摘要翻译： 在一个实施例中，用于多节点计算机系统中的节点的存储器控​​制器包括逻辑和控制单元。 逻辑被配置为确定与内部控制器在内部网络互连上接收到的请求对应的地址是远程地址还是本地地址。 分配节点中的存储器的第一部分以存储远程数据的副本，并且剩余部分存储本地数据。 控制单元被配置为将写回数据写入第一部分中的位置。 回写数据对应于具有由逻辑检测到的相关联的远程地址的内部网络互连的回写请求。 控制单元被配置为确定响应于相关联的远程地址的位置和识别存储器中的第一部分的一个或多个指示符。

公开(公告)号：US07373461B2

公开(公告)日：2008-05-13

申请号：US11413244

申请日：2006-04-28

申请人： Håkan E. Zeffer ,  Erik E. Hagersten

发明人： Håkan E. Zeffer ,  Erik E. Hagersten

IPC分类号： G06F12/00

CPC分类号： G06F12/0817 ,  G06F12/0837 ,  G06F2212/507

摘要： In one embodiment, a node for a multi-node computer system comprises a coherence directory configured to store coherence states for coherence units in a local memory of the node and a coherence controller configured to receive a coherence request for a requested coherence unit. The requested coherence unit is included in a memory region that includes at least two coherence units, and the coherence controller is configured to read coherence states corresponding to two or more coherence units from the coherence directory responsive to the coherence request. The two or more coherence units are included in a previously-accessed memory region, and the coherence controller is configured to provide the requested coherence unit with a predicted coherence state responsive to the coherence states in the previously accessed memory region.

摘要翻译： 在一个实施例中，用于多节点计算机系统的节点包括被配置为存储节点的本地存储器中的相干单元的相干状态的相干目录和被配置为接收对所请求的相干单元的一致性请求的相干控制器。 所请求的相干单元被包括在包括至少两个相干单元的存储器区域中，并且相干控制器被配置为响应于相干请求从相干目录读取与两个或更多个相干单元相对应的相干状态。 两个或更多个相干单元被包括在先前访问的存储器区域中，并且相干控制器被配置为响应于先前访问的存储器区域中的相干状态来向所请求的相干单元提供预测相干状态。

公开(公告)号：US07480770B2

公开(公告)日：2009-01-20

申请号：US11452647

申请日：2006-06-14

申请人： Håkan E. Zeffer ,  Anders Landin

发明人： Håkan E. Zeffer ,  Anders Landin

IPC分类号： G06F12/00

CPC分类号： G06F12/0828

摘要： In one embodiment, a node for a multi-node computer system comprises a coherence directory and a coherence controller. The coherence directory comprises a plurality of entries, wherein each entry corresponds to a respective coherence unit and stores a state identifying which nodes in the computer system are storing a copy of the coherence unit and further identifying a coherence state of the coherence unit according to a coherence protocol implemented in the computer system. Coupled to the directory and coupled to receive a first request for a requested coherence unit having a first entry in the coherence directory, the coherence controller is coupled to receive a second request for the requested coherence unit. The coherence controller is configured to selectively initiate coherence activity for the second request, if coherence activity for the first request is not yet complete, dependent on a type of the second request.

摘要翻译： 在一个实施例中，用于多节点计算机系统的节点包括相干目录和相干控制器。 相干目录包括多个条目，其中每个条目对应于相应的相干单元，并且存储识别计算机系统中的哪些节点正在存储相干单元的副本的状态，并且进一步根据相关单元识别相干单元的相干状态 在计算机系统中实现一致性协议。 耦合到目录并被耦合以接收对于在相干目录中具有第一条目的所请求的相干单元的第一请求，所述相干控制器被耦合以接收对所请求的相干单元的第二请求。 如果第一请求的一致性活动尚未完成，则相干控制器被配置为选择性地启动第二请求的相干活动，这取决于第二请求的类型。

公开(公告)号：US07412567B2

公开(公告)日：2008-08-12

申请号：US11413243

申请日：2006-04-28

申请人： Håkan E. Zeffer ,  Erik E. Hagersten ,  Anders Landin ,  Shailender Chaudhry ,  Paul N. Loewenstein ,  Robert E. Cypher ,  Zoran Radovic

发明人： Håkan E. Zeffer ,  Erik E. Hagersten ,  Anders Landin ,  Shailender Chaudhry ,  Paul N. Loewenstein ,  Robert E. Cypher ,  Zoran Radovic

IPC分类号： G06F12/00

CPC分类号： G06F12/0815 ,  G06F12/0808 ,  G06F12/0822 ,  G06F12/0897

摘要： In one embodiment, a processor comprises a coherence trap unit and a trap logic coupled to the coherence trap unit. The coherence trap unit is also coupled to receive data accessed in response to the processor executing a memory operation. The coherence trap unit is configured to detect that the data matches a designated value indicating that a coherence trap is to be initiated to coherently perform the memory operation. The trap logic is configured to trap to a designated software routine responsive to the coherence trap unit detecting the designated value. In some embodiments, a cache tag in a cache may track whether or not the corresponding cache line has the designated value, and the cache tag may be used to trigger a trap in response to an access to the corresponding cache line.

摘要翻译： 在一个实施例中，处理器包括相干陷阱单元和耦合到相干陷波单元的陷波逻辑。 相干陷阱单元还被耦合以接收响应于处理器执行存储器操作而访问的数据。 相干陷阱单元被配置为检测数据与指示要发起的相干陷阱的指定值匹配以相干地执行存储器操作。 陷阱逻辑被配置为响应于相干陷阱单元检测到指定值而陷入指定的软件例行程序。 在一些实施例中，高速缓存中的高速缓存标签可以跟踪对应的高速缓存行是否具有指定值，并且可以使用高速缓存标签来响应对对应的高速缓存行的访问来触发陷阱。