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公开(公告)号：US07412567B2
公开(公告)日：2008-08-12
申请号：US11413243
申请日：2006-04-28
申请人： Håkan E. Zeffer , Erik E. Hagersten , Anders Landin , Shailender Chaudhry , Paul N. Loewenstein , Robert E. Cypher , Zoran Radovic
发明人： Håkan E. Zeffer , Erik E. Hagersten , Anders Landin , Shailender Chaudhry , Paul N. Loewenstein , Robert E. Cypher , Zoran Radovic
IPC分类号： G06F12/00
CPC分类号： G06F12/0815 , G06F12/0808 , G06F12/0822 , G06F12/0897
摘要： In one embodiment, a processor comprises a coherence trap unit and a trap logic coupled to the coherence trap unit. The coherence trap unit is also coupled to receive data accessed in response to the processor executing a memory operation. The coherence trap unit is configured to detect that the data matches a designated value indicating that a coherence trap is to be initiated to coherently perform the memory operation. The trap logic is configured to trap to a designated software routine responsive to the coherence trap unit detecting the designated value. In some embodiments, a cache tag in a cache may track whether or not the corresponding cache line has the designated value, and the cache tag may be used to trigger a trap in response to an access to the corresponding cache line.
摘要翻译： 在一个实施例中，处理器包括相干陷阱单元和耦合到相干陷波单元的陷波逻辑。 相干陷阱单元还被耦合以接收响应于处理器执行存储器操作而访问的数据。 相干陷阱单元被配置为检测数据与指示要发起的相干陷阱的指定值匹配以相干地执行存储器操作。 陷阱逻辑被配置为响应于相干陷阱单元检测到指定值而陷入指定的软件例行程序。 在一些实施例中，高速缓存中的高速缓存标签可以跟踪对应的高速缓存行是否具有指定值，并且可以使用高速缓存标签来响应对对应的高速缓存行的访问来触发陷阱。
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2.发明授权DRAM remote access cache in local memory in a distributed shared memory system 有权DRAM远程访问缓存在分布式共享内存系统的本地内存中公开(公告)号：US07509460B2
公开(公告)日：2009-03-24
申请号：US11417640
申请日：2006-05-04
CPC分类号： G06F12/0815
摘要： In one embodiment, a memory controller for a node in a multi-node computer system comprises logic and a control unit. The logic is configured to determine if an address corresponding to a request received by the memory controller on an intranode interconnect is a remote address or a local address. A first portion of the memory in the node is allocated to store copies of remote data and a remaining portion stores local data. The control unit is configured to write writeback data to a location in the first portion. The writeback data corresponds to a writeback request from the intranode interconnect that has an associated remote address detected by the logic. The control unit is configured to determine the location responsive to the associated remote address and one or more indicators that identify the first portion in the memory.
摘要翻译： 在一个实施例中，用于多节点计算机系统中的节点的存储器控制器包括逻辑和控制单元。 逻辑被配置为确定与内部控制器在内部网络互连上接收到的请求对应的地址是远程地址还是本地地址。 分配节点中的存储器的第一部分以存储远程数据的副本，并且剩余部分存储本地数据。 控制单元被配置为将写回数据写入第一部分中的位置。 回写数据对应于具有由逻辑检测到的相关联的远程地址的内部网络互连的回写请求。 控制单元被配置为确定响应于相关联的远程地址的位置和识别存储器中的第一部分的一个或多个指示符。
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3.发明授权Multi-node computer system implementing global access state dependent transactions 有权实现全局访问状态相关事务的多节点计算机系统公开(公告)号：US07606978B2
公开(公告)日：2009-10-20
申请号：US10821394
申请日：2004-04-09
IPC分类号： G06F12/00
CPC分类号： G06F12/0817 , G06F12/0813 , G06F12/0815
摘要： A node in a multi-node system includes a memory, an active device that includes a cache, an interface that sends and receives coherency messages on an inter-node network coupling the node to another node, and an address network that communicates address packets between the devices in the node. In response to receiving a coherency message from the other node requesting an access right to a coherency unit, the interface sends an address packet on the address network. The address packet is a first type of address packet if the coherency unit is in the modified global access state in the node and a second type of address packet otherwise. If the active device is the owner of the coherency unit, the active device responds to the first type of address packet and ignores the second type of address packet.
摘要翻译： 多节点系统中的节点包括存储器，包括高速缓存的活动设备，在将节点耦合到另一节点的节点间网络上发送和接收一致性消息的接口，以及传送地址分组之间的地址网络 节点中的设备。 响应于从其他节点接收请求对一致性单元的访问权限的一致性消息，该接口在地址网络上发送地址分组。 如果一致性单元在节点中处于修改的全局访问状态，否则地址分组是第一类型的地址分组，而另一种类型的地址分组。 如果活动设备是一致性单元的所有者，则活动设备响应于第一类型的地址分组，并且忽略第二类型的地址分组。
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4.发明授权Multi-node computer system with proxy transaction to read data from a non-owning memory device 有权具有代理事务的多节点计算机系统从非拥有的存储设备读取数据公开(公告)号：US08010749B2
公开(公告)日：2011-08-30
申请号：US10821372
申请日：2004-04-09
CPC分类号： G06F12/0817 , G06F12/0813
摘要： A node includes several devices including a memory, an active device, and an interface configured to send and receive coherency messages on an inter-node network coupling the node to another node, as well as an address network and a data network. In response to receiving a coherency message requesting an access right to a coherency unit, the interface is configured to send a first type of address packet on the address network if the global access state of the coherency unit within the node is the modified state and a second type of address packet otherwise. The memory is configured to respond to receipt of the second type of address packet by sending a data packet on the data network, regardless of whether the memory currently has an ownership responsibility for the coherency unit.
摘要翻译： 节点包括若干设备，包括存储器，活动设备和被配置为在将节点耦合到另一节点的节点间网络以及地址网络和数据网络上发送和接收一致性消息的接口。 响应于接收到请求对一致性单元的访问权限的一致性消息，该接口被配置为如果节点内的一致性单元的全局访问状态是修改状态，则该接口被配置为在地址网络上发送第一类型的地址分组，并且 否则第二种类型的地址包。 存储器被配置为通过在数据网络上发送数据分组来响应第二类型的地址分组的接收，而不管存储器当前是否具有对于一致性单元的所有权责任。
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5.发明授权Multi-node system with split ownership and access right coherence mechanism 有权具有分割所有权和访问权限一致性机制的多节点系统公开(公告)号：US07529893B2
公开(公告)日：2009-05-05
申请号：US10821564
申请日：2004-04-09
CPC分类号： G06F12/0828
摘要： A system may include multiple nodes, and each node may include a processing subsystem and an interface that are coupled by an address network and a data network. The nodes' interfaces may communicate over an inter-node network. Each processing subsystem may transition an access right to a coherency unit in response to a data packet on the data network and transition an ownership responsibility for the coherency unit in response to an address packet on the address network such that the access right transitions at a different time than the ownership responsibility transitions. An interface within a node may be configured to delay providing a data packet on the node's data network until the interface receives an indication that shared copies of the coherency unit in other nodes have been invalidated.
摘要翻译： 系统可以包括多个节点，并且每个节点可以包括由地址网络和数据网络耦合的处理子系统和接口。 节点的接口可以通过节点间网络进行通信。 响应于数据网络上的数据分组，每个处理子系统可以将访问权限转换到一致性单元，并响应于地址网络上的地址分组转移一致性单元的所有权责任，使得访问权限在不同的 时间比所有权责任过渡。 节点内的接口可以被配置为延迟在节点的数据网络上提供数据分组，直到接口接收到其他节点中的一致性单元的共享副本已经被无效的指示。
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6.发明授权Multi-node system in which global address generated by processing subsystem includes global to local translation information 有权多节点系统，其中由处理子系统生成的全局地址包括全局到本地的翻译信息公开(公告)号：US07360056B2
公开(公告)日：2008-04-15
申请号：US10817630
申请日：2004-04-02
CPC分类号： G06F12/1072 , G06F12/0822
摘要： A system may include a plurality of nodes. Each node may include one or more active devices coupled to one or more memory subsystems. An active device included in one of the nodes includes a memory management unit configured to receive a virtual address generated within that active device and to responsively output a global address identifying a coherency unit. A portion of the global address identifies a translation function. A memory subsystem included in the node is configured to perform the translation function identified by the portion of the global address on an additional portion of the global address in order to obtain a local physical address of the coherency unit. Each active device included in the node is configured to use the portion of the global address identifying the translation function when determining whether a local copy of the coherency unit is currently stored in a cache associated with that active device.
摘要翻译： 系统可以包括多个节点。 每个节点可以包括耦合到一个或多个存储器子系统的一个或多个活动设备。 包括在其中一个节点中的活动设备包括：存储器管理单元，被配置为接收在该有源设备内生成的虚拟地址，并响应地输出标识一致性单元的全局地址。 全局地址的一部分标识翻译功能。 包括在节点中的存储器子系统被配置为在全局地址的附加部分上执行由全局地址的部分标识的翻译功能，以便获得一致性单元的本地物理地址。 包括在节点中的每个活动设备被配置为当确定一致性单元的本地副本当前是否存储在与该有源设备相关联的高速缓存中时，使用标识翻译功能的全局地址的部分。
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公开(公告)号：US08024526B2
公开(公告)日：2011-09-20
申请号：US10821371
申请日：2004-04-09
IPC分类号： G06F12/00
CPC分类号： G06F12/0813 , G06F12/0817
摘要： A system may include several nodes coupled by an inter-node network configured to convey coherency messages between the nodes. Each node may include several active devices coupled by an address network and a data network. The nodes implement a coherency protocol such that if an active device in one of the nodes has an ownership responsibility for a coherency unit, no active device in any of the other nodes has a valid access right to the coherency unit. For example, if a node receives a coherency message requesting read access to a coherency unit from another node, the node may respond by conveying a proxy address packet, receipt of which removes ownership, on the node's address network to an owning active device. In contrast, the active device's ownership responsibility may not be removed in response to a device within the same node requesting read access to the coherency unit.
摘要翻译： 系统可以包括由节点间网络耦合的若干节点，其被配置为在节点之间传送一致性消息。 每个节点可以包括由地址网络和数据网络耦合的若干有效设备。 节点实现一致性协议，使得如果节点之一中的活动设备对于一致性单元具有所有权责任，则任何其他节点中的任何活动设备都不具有对一致性单元的有效访问权限。 例如，如果节点接收到请求对来自另一个节点的一致性单元的读取访问的一致性消息，则该节点可以通过将节点的地址网络上的所有权的所有者的所有权传送给拥有的活动设备来进行响应。 相比之下，活动设备的所有权责任可能不会被移除，以响应同一个节点内请求对一致性单元的读取访问的设备。
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公开(公告)号：US07120756B2
公开(公告)日：2006-10-10
申请号：US10610520
申请日：2003-06-30
IPC分类号： G06F12/06
CPC分类号： G06F12/0815
摘要： A computer system includes a system memory and a plurality of active devices configured to access data associated with the system memory through an address network and a data network. Each of the active devices may be configured to cache data, and may include a promise array. Transitions in ownership of the given block may occur at a different time than the time at which the access right to the given block is changed. The promise array of an active device is provided to store information identifying an unreceived data packet to be conveyed to another device in response to a pending transaction to a cache block for which the active device is an owner. Each active device may be configured to have at most one outstanding transaction for each cache block.
摘要翻译： 计算机系统包括系统存储器和被配置为通过地址网络和数据网络访问与系统存储器相关联的数据的多个主动设备。 每个活动设备可以被配置为高速缓存数据，并且可以包括承诺阵列。 给定块的所有权转换可能发生在与给定块的访问权限发生更改的时间不同的时间内。 活动设备的承诺阵列被提供用于存储标识待传送到另一设备的未接收的数据分组的信息，以响应于到达活动设备是所有者的高速缓存块的未决事务。 每个活动设备可以被配置为对于每个高速缓存块具有至多一个未完成的事务。
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公开(公告)号：US07373461B2
公开(公告)日：2008-05-13
申请号：US11413244
申请日：2006-04-28
申请人： Håkan E. Zeffer , Erik E. Hagersten
发明人： Håkan E. Zeffer , Erik E. Hagersten
IPC分类号： G06F12/00
CPC分类号： G06F12/0817 , G06F12/0837 , G06F2212/507
摘要： In one embodiment, a node for a multi-node computer system comprises a coherence directory configured to store coherence states for coherence units in a local memory of the node and a coherence controller configured to receive a coherence request for a requested coherence unit. The requested coherence unit is included in a memory region that includes at least two coherence units, and the coherence controller is configured to read coherence states corresponding to two or more coherence units from the coherence directory responsive to the coherence request. The two or more coherence units are included in a previously-accessed memory region, and the coherence controller is configured to provide the requested coherence unit with a predicted coherence state responsive to the coherence states in the previously accessed memory region.
摘要翻译： 在一个实施例中，用于多节点计算机系统的节点包括被配置为存储节点的本地存储器中的相干单元的相干状态的相干目录和被配置为接收对所请求的相干单元的一致性请求的相干控制器。 所请求的相干单元被包括在包括至少两个相干单元的存储器区域中，并且相干控制器被配置为响应于相干请求从相干目录读取与两个或更多个相干单元相对应的相干状态。 两个或更多个相干单元被包括在先前访问的存储器区域中，并且相干控制器被配置为响应于先前访问的存储器区域中的相干状态来向所请求的相干单元提供预测相干状态。
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公开(公告)号：US07529844B2
公开(公告)日：2009-05-05
申请号：US10422454
申请日：2003-04-24
申请人： Zoran Radovic , Erik E. Hagersten
发明人： Zoran Radovic , Erik E. Hagersten
IPC分类号： G06F15/16
CPC分类号： G06F9/526
摘要： A method for controlling a software lock acquirable by processors in a plurality of nodes of a multiprocessing system is disclosed. The method comprises a first processor of a first node of the plurality of nodes acquiring the lock, and the first processor selectively releasing the lock in a first state that allows other processors within the first node to acquire the lock but that prevents processors in a remote node of the plurality of nodes from obtaining the lock. In another embodiment, a method comprises a first processor of a first node attempting to acquire the lock, the first processor determining whether another processor within the same node is remotely spinning on the lock, and the first processor remotely spinning on the lock in response to determining that another processor in the same node is not remotely spinning on the software lock.
摘要翻译： 公开了一种用于控制由多处理系统的多个节点中的处理器获取的软件锁定的方法。 该方法包括：多个节点中的第一节点的第一处理器获取锁定，并且第一处理器选择性地释放锁，该第一状态允许第一节点内的其他处理器获取锁定，但是防止处于远程 多个节点的节点获得锁定。 在另一个实施例中，一种方法包括尝试获取锁的第一节点的第一处理器，第一处理器确定同一节点内的另一个处理器是否在锁上进行远程旋转，并且第一处理器响应于 确定同一节点中的另一个处理器不会在软件锁上远程旋转。
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