公开(公告)号：US07412567B2

公开(公告)日：2008-08-12

申请号：US11413243

申请日：2006-04-28

申请人： Håkan E. Zeffer ,  Erik E. Hagersten ,  Anders Landin ,  Shailender Chaudhry ,  Paul N. Loewenstein ,  Robert E. Cypher ,  Zoran Radovic

发明人： Håkan E. Zeffer ,  Erik E. Hagersten ,  Anders Landin ,  Shailender Chaudhry ,  Paul N. Loewenstein ,  Robert E. Cypher ,  Zoran Radovic

IPC分类号： G06F12/00

CPC分类号： G06F12/0815 ,  G06F12/0808 ,  G06F12/0822 ,  G06F12/0897

摘要： In one embodiment, a processor comprises a coherence trap unit and a trap logic coupled to the coherence trap unit. The coherence trap unit is also coupled to receive data accessed in response to the processor executing a memory operation. The coherence trap unit is configured to detect that the data matches a designated value indicating that a coherence trap is to be initiated to coherently perform the memory operation. The trap logic is configured to trap to a designated software routine responsive to the coherence trap unit detecting the designated value. In some embodiments, a cache tag in a cache may track whether or not the corresponding cache line has the designated value, and the cache tag may be used to trigger a trap in response to an access to the corresponding cache line.

摘要翻译： 在一个实施例中，处理器包括相干陷阱单元和耦合到相干陷波单元的陷波逻辑。 相干陷阱单元还被耦合以接收响应于处理器执行存储器操作而访问的数据。 相干陷阱单元被配置为检测数据与指示要发起的相干陷阱的指定值匹配以相干地执行存储器操作。 陷阱逻辑被配置为响应于相干陷阱单元检测到指定值而陷入指定的软件例行程序。 在一些实施例中，高速缓存中的高速缓存标签可以跟踪对应的高速缓存行是否具有指定值，并且可以使用高速缓存标签来响应对对应的高速缓存行的访问来触发陷阱。

公开(公告)号：US20070255907A1

公开(公告)日：2007-11-01

申请号：US11413243

申请日：2006-04-28

申请人： Hakan Zeffer ,  Erik Hagersten ,  Anders Landin ,  Shailender Chaudhry ,  Paul Loewenstein ,  Robert Cypher ,  Zoran Radovic

发明人： Hakan Zeffer ,  Erik Hagersten ,  Anders Landin ,  Shailender Chaudhry ,  Paul Loewenstein ,  Robert Cypher ,  Zoran Radovic

IPC分类号： G06F13/28

CPC分类号： G06F12/0815 ,  G06F12/0808 ,  G06F12/0822 ,  G06F12/0897

摘要： In one embodiment, a processor comprises a coherence trap unit and a trap logic coupled to the coherence trap unit. The coherence trap unit is also coupled to receive data accessed in response to the processor executing a memory operation. The coherence trap unit is configured to detect that the data matches a designated value indicating that a coherence trap is to be initiated to coherently perform the memory operation. The trap logic is configured to trap to a designated software routine responsive to the coherence trap unit detecting the designated value. In some embodiments, a cache tag in a cache may track whether or not the corresponding cache line has the designated value, and the cache tag may be used to trigger a trap in response to an access to the corresponding cache line.

摘要翻译： 在一个实施例中，处理器包括相干陷阱单元和耦合到相干陷波单元的陷波逻辑。 相干陷阱单元还被耦合以接收响应于处理器执行存储器操作而访问的数据。 相干陷阱单元被配置为检测数据与指示要发起的相干陷阱的指定值相匹配以相干地执行存储器操作。 陷阱逻辑被配置为响应于相干陷阱单元检测到指定值而陷入指定的软件例行程序。 在一些实施例中，高速缓存中的高速缓存标签可以跟踪对应的高速缓存行是否具有指定值，并且可以使用高速缓存标签来响应对对应的高速缓存行的访问来触发陷阱。

公开(公告)号：US20090019231A1

公开(公告)日：2009-01-15

申请号：US11775693

申请日：2007-07-10

申请人： Robert E. Cypher ,  Shailender Chaudhry ,  Anders Landin

发明人： Robert E. Cypher ,  Shailender Chaudhry ,  Anders Landin

IPC分类号： G06F12/08

CPC分类号： G06F12/08 ,  G06F12/0842 ,  G06F12/1045 ,  G06F12/1081

摘要： Embodiments of the present invention implement virtual transactional memory using cache line marking. The system starts by executing a starvation-avoiding transaction for a thread. While executing the starvation-avoiding transaction, the system places starvation-avoiding load-marks on cache lines which are loaded from and places starvation-avoiding store-marks on cache lines which are stored to. Next, while swapping a page out of a memory and to a disk during the starvation-avoiding transaction, the system determines if one or more cache lines in the page have a starvation-avoiding load-mark or a starvation-avoiding store-mark. If so, upon swapping the page into the memory from the disk, the system places a starvation-avoiding load-mark on each cache line that had a starvation-avoiding load-mark and places a starvation-avoiding store-mark on each cache line that had a starvation-avoiding store-mark.

摘要翻译： 本发明的实施例使用高速缓存行标记来实现虚拟事务存储器。 系统通过执行线程的避免饥饿事务来启动。 在执行避免饥饿事务的同时，系统会在加载的缓存行上放置饥饿 - 避免加载标记，并将存储在缓存行上的饥饿 - 避免存储标记放置在缓存行上。 接下来，当在饥饿 - 避免交易期间将页面从存储器切换到磁盘时，系统确定页面中的一个或多个高速缓存行是否具有避免饥饿负载标记或避免饥饿的存储标记。 如果是这样，当将页面从磁盘交换到内存中时，系统会在每个具有饥饿 - 避免加载标记的缓存行上放置一个避免饥饿的加载标记，并在每条缓存行上放置一个避免饥饿的商标 有一个饥饿的避免商标。

公开(公告)号：US07676636B2

公开(公告)日：2010-03-09

申请号：US11775693

申请日：2007-07-10

申请人： Robert E. Cypher ,  Shailender Chaudhry ,  Anders Landin

发明人： Robert E. Cypher ,  Shailender Chaudhry ,  Anders Landin

IPC分类号： G06F12/08

CPC分类号： G06F12/08 ,  G06F12/0842 ,  G06F12/1045 ,  G06F12/1081

摘要： Embodiments of the present invention implement virtual transactional memory using cache line marking. The system starts by executing a starvation-avoiding transaction for a thread. While executing the starvation-avoiding transaction, the system places starvation-avoiding load-marks on cache lines which are loaded from and places starvation-avoiding store-marks on cache lines which are stored to. Next, while swapping a page out of a memory and to a disk during the starvation-avoiding transaction, the system determines if one or more cache lines in the page have a starvation-avoiding load-mark or a starvation-avoiding store-mark. If so, upon swapping the page into the memory from the disk, the system places a starvation-avoiding load-mark on each cache line that had a starvation-avoiding load-mark and places a starvation-avoiding store-mark on each cache line that had a starvation-avoiding store-mark.

摘要翻译： 本发明的实施例使用高速缓存行标记来实现虚拟事务存储器。 系统通过执行线程的避免饥饿事务来启动。 在执行避免饥饿事务的同时，系统会在加载的缓存行上放置饥饿 - 避免加载标记，并将存储在缓存行上的饥饿 - 避免存储标记放置在缓存行上。 接下来，当在饥饿 - 避免交易期间将页面从存储器切换到磁盘时，系统确定页面中的一个或多个高速缓存行是否具有避免饥饿负载标记或避免饥饿的存储标记。 如果是这样，当将页面从磁盘交换到内存中时，系统会在每个具有饥饿 - 避免加载标记的缓存行上放置一个避免饥饿的加载标记，并在每条缓存行上放置一个避免饥饿的商标 有一个饥饿的避免商标。

公开(公告)号：US20100325374A1

公开(公告)日：2010-12-23

申请号：US12486138

申请日：2009-06-17

申请人： Robert E. Cypher ,  Shailender Chaudhry ,  Anders Landin ,  Haakan E. Zeffer

发明人： Robert E. Cypher ,  Shailender Chaudhry ,  Anders Landin ,  Haakan E. Zeffer

IPC分类号： G06F12/10 ,  G06F12/02 ,  G06F12/00

CPC分类号： G06F12/0607 ,  G06F12/0646 ,  G06F12/0813 ,  G06F12/0817 ,  G06F12/10

摘要： Embodiments of the present invention provide a system that dynamically reconfigures memory. During operation, the system determines that a virtual memory page is to be reconfigured from an original virtual-address-to-physical-address mapping to a new virtual-address-to-physical-address mapping. The system then determines a new real address mapping for a set of virtual addresses in the virtual memory page by selecting a range of real addresses for the virtual addresses that are arranged according to the new virtual-address-to-physical-address mapping. Next, the system temporarily disables accesses to the virtual memory page. Then, the system copies data from real address locations indicated by the original virtual-address-to-physical-address mapping to real address locations indicated by the new virtual-address-to-physical-address mapping. Next, the system updates the real-address-to-physical-address mapping for the page, and re-enables accesses to the virtual memory page.

摘要翻译： 本发明的实施例提供一种动态重新配置存储器的系统。 在操作期间，系统确定虚拟内存页面将被重新配置为从原始虚拟地址到物理地址映射到新的虚拟地址到物理地址映射。 然后，系统通过选择根据新的虚拟地址到物理地址映射排列的虚拟地址的实际地址的范围来确定虚拟存储器页面中的一组虚拟地址的新的真实地址映射。 接下来，系统暂时禁用对虚拟内存页的访问。 然后，系统将由原始虚拟地址到物理地址映射指示的实际地址位置的数据复制到由新的虚拟地址到物理地址映射指示的实际地址位置。 接下来，系统更新页面的实际地址到物理地址映射，并重新启用对虚拟内存页的访问。

公开(公告)号：US07797491B2

公开(公告)日：2010-09-14

申请号：US11591225

申请日：2006-10-31

申请人： Robert E. Cypher ,  Shailender Chaudhry

发明人： Robert E. Cypher ,  Shailender Chaudhry

IPC分类号： G06F12/00 ,  G06F13/00

CPC分类号： G06F12/0842 ,  G06F9/3004 ,  G06F9/383 ,  G06F9/3834 ,  G06F9/3851

摘要： One embodiment of the present invention provides a system that facilitates load reordering through cacheline marking. During operation, the system receives a load operation to be executed. Next, the system determines whether a cacheline for the load has been load-marked by a thread which is performing the load. If so, the system performs the load. Otherwise, the system obtains the cacheline and subsequently attempts to load-mark the cacheline. If the cacheline is successfully load-marked, the system performs the load.

摘要翻译： 本发明的一个实施例提供一种通过高速缓存行标记来促进负载重新排序的系统。 在操作期间，系统接收要执行的加载操作。 接下来，系统确定负载的高速缓存线是否由正在执行负载的线程加载标记。 如果是这样，系统执行负载。 否则，系统将获取缓存线，并随后尝试加载标记缓存线。 如果缓存线已成功加载标记，系统将执行加载。

公开(公告)号：US07594100B2

公开(公告)日：2009-09-22

申请号：US11540257

申请日：2006-09-29

申请人： Robert E. Cypher ,  Shailender Chaudhry

发明人： Robert E. Cypher ,  Shailender Chaudhry

IPC分类号： G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F15/00

CPC分类号： G06F9/3834 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3867 ,  G06F12/0897

摘要： One embodiment of the present invention provides a store queue that applies the stores to a memory subsystem in program order. This store queue includes a content-addressable memory (CAM), which holds pending stores and facilitates looking up stores based on addresses for the stores, wherein the CAM does not keep track of program order between stores to different addresses. The store queue also includes a program-order queue which keeps track of program order between the stores in the CAM and thereby facilitates applying the stores to the memory subsystem in program order. In a variation on this embodiment, the CAM is a priority CAM which holds separate copies of multiple stores with identical addresses, and when a lookup based on an address matches multiple stores, returns the youngest matching store.

摘要翻译： 本发明的一个实施例提供一种存储队列，其以程序顺序将存储应用于存储器子系统。 该存储队列包括内容可寻址存储器（CAM），其保存挂起的存储并且便于基于用于存储的地址来查找存储，其中，CAM不会将存储之间的程序顺序跟踪到不同的地址。 存储队列还包括程序顺序队列，其跟踪CAM中的存储之间的程序顺序，从而有助于以程序顺序将存储应用于存储器子系统。 在本实施例的变型中，CAM是优先CAM，其保存具有相同地址的多个商店的分开的副本，并且当基于地址的查找匹配多个商店时，返回最年轻的匹配商店。

公开(公告)号：US20090113131A1

公开(公告)日：2009-04-30

申请号：US11924742

申请日：2007-10-26

申请人： Robert E. Cypher ,  Shailender Chaudhry

发明人： Robert E. Cypher ,  Shailender Chaudhry

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0897 ,  G06F12/0842 ,  G06F12/126

摘要： Embodiments of the present invention provide a system that handles load-marked and store-marked cache lines. Upon asserting a load-mark or a store-mark for a cache line during a given phase of operation, the system adds an entry to a private buffer and in doing so uses an address of the cache line as a key for the entry in the private buffer. The system also updates the entry in the private buffer with information about the load-mark or store-mark and uses pointers for the entry and for the last entry added to the private buffer to add the entry to a sequence of private buffer entries placed during the phase of operation. The system then uses the entries in the private buffer to remove the load-marks and store-marks from cache lines when the phase of operation is completed.

摘要翻译： 本发明的实施例提供一种处理负载标记和存储标记的高速缓存行的系统。 在给定的操作阶段中断定高速缓存行的加载标记或存储标记时，系统将一个条目添加到专用缓冲区，并且在这样做时使用高速缓存行的地址作为该条目的密钥 私人缓存。 系统还使用有关加载标记或存储标记的信息更新专用缓冲区中的条目，并使用条目的指针和添加到专用缓冲区的最后一个条目将条目添加到放置在 操作阶段。 当操作阶段完成时，系统将使用专用缓冲区中的条目从缓存行中删除加载标记和存储标记。

公开(公告)号：US20090019272A1

公开(公告)日：2009-01-15

申请号：US11774705

申请日：2007-07-09

申请人： Robert E. Cypher ,  Shailender Chaudhry

发明人： Robert E. Cypher ,  Shailender Chaudhry

IPC分类号： G06F9/312

CPC分类号： G06F9/3834 ,  G06F9/3842

摘要： Embodiments of the present invention provide a system that buffers stores on a processor that supports speculative execution. The system starts by buffering a store into an entry in the store queue during a speculative execution mode. If an entry for the store does not already exist in the store queue, the system writes the store into an available entry in the store queue and updates a byte mask for the entry. Otherwise, if an entry for the store already exists in the store queue, the system merges the store into the existing entry in the store queue and updates the byte mask for the entry to include information about the newly merged store. The system then forwards the data from the store queue to subsequent dependent loads.

摘要翻译： 本发明的实施例提供一种缓冲存储在支持推测执行的处理器上的系统的系统。 在推测执行模式期间，系统通过将存储缓存到存储队列中的条目来启动。 如果商店中的条目不存在于商店队列中，则系统将商店写入存储队列中的可用条目，并更新条目的字节掩码。 否则，如果商店的条目已经存在于存储队列中，则系统将存储合并到存储队列中的现有条目中，并更新条目的字节掩码以包括关于新合并存储的信息。 然后，系统将数据从存储队列转发到后续的相关负载。

公开(公告)号：US20080082738A1

公开(公告)日：2008-04-03

申请号：US11540257

申请日：2006-09-29

申请人： Robert E. Cypher ,  Shailender Chaudhry

发明人： Robert E. Cypher ,  Shailender Chaudhry

IPC分类号： G06F12/00

CPC分类号： G06F9/3834 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3867 ,  G06F12/0897

摘要： One embodiment of the present invention provides a store queue that applies the stores to a memory subsystem in program order. This store queue includes a content-addressable memory (CAM), which holds pending stores and facilitates looking up stores based on addresses for the stores, wherein the CAM does not keep track of program order between stores to different addresses. The store queue also includes a program-order queue which keeps track of program order between the stores in the CAM and thereby facilitates applying the stores to the memory subsystem in program order. In a variation on this embodiment, the CAM is a priority CAM which holds separate copies of multiple stores with identical addresses, and when a lookup based on an address matches multiple stores, returns the youngest matching store.

摘要翻译： 本发明的一个实施例提供一种存储队列，其以程序顺序将存储应用于存储器子系统。 该存储队列包括内容可寻址存储器（CAM），其保存挂起的存储并且便于基于用于存储的地址来查找存储，其中，CAM不会将存储之间的程序顺序跟踪到不同的地址。 存储队列还包括程序顺序队列，其跟踪CAM中的存储之间的程序顺序，从而有助于以程序顺序将存储应用于存储器子系统。 在本实施例的变型中，CAM是优先CAM，其保存具有相同地址的多个商店的分开的副本，并且当基于地址的查找匹配多个商店时，返回最年轻的匹配商店。