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    Implementing a constant in FPGA code
    12.
    发明授权
    Implementing a constant in FPGA code 有权

    公开(公告)号：US10318687B2

    公开(公告)日：2019-06-11

    申请号：US14753439

    申请日：2015-06-29

    Applicant: dSPACE digital signal processing and control engineering GmbH

    Inventor： Heiko Kalte ,  Lukas Funke

    IPC: G06F7/60 ,  G06F17/10 ,  G06F17/50 ,  G06F8/30

    Abstract: A method for generating FPGA code based on an FPGA model with at least one signal value that is modeled as a constant. A constant is inserted with a predefined signal value in the FPGA model. A switching variable is set in the FPGA model for switching between a normal mode and a calibration mode for the FPGA code. The FPGA code is generated for the FPGA model having the implementation of the constants in the FPGA code, wherein the implementation of the constants when the switching variable is set for normal mode includes the implementation of the constants as a fixed value in the FPGA code, and the implementation of the constants when the switching variable is set for calibration mode includes the implementation of the constants as a modifiable signal value in the FPGA code. A method for calibrating an FPGA model is also provided.

    METHOD FOR READING OUT VARIABLES FROM AN FPGA
    13.
    发明申请
    METHOD FOR READING OUT VARIABLES FROM AN FPGA 审中-公开

    公开(公告)号：US20190138310A1

    公开(公告)日：2019-05-09

    申请号：US16182637

    申请日：2018-11-07

    Applicant: dSPACE digital signal processing and control engineering GmbH

    Inventor： Heiko Kalte ,  Dominik Lubeley

    IPC: G06F9/30 ,  G06F17/50

    Abstract: A method for reading variables from a Field Programmable Gate Array (FPGA) at runtime includes: calculating, in the FPGA, a first variable, wherein the first variable is associated with a first shadow register and a second shadow register, and wherein the first variable is associated with a first measurement grid and with a second measurement grid; synchronously storing, at a first point in time, all variables associated with the first measurement grid in shadow registers associated with the respective variables; synchronously storing, at a second point in time, all variables associated with the second measurement grid in shadow registers associated with the respective variables; and reading out the shadow registers independently of one another.

    Determination of signals for readback from FPGA
    14.
    发明授权
    Determination of signals for readback from FPGA 有权

    公开(公告)号：US10223077B2

    公开(公告)日：2019-03-05

    申请号：US14863494

    申请日：2015-09-24

    Applicant: dSPACE digital signal processing and control engineering GmbH

    Inventor： Heiko Kalte ,  Lukas Funke

    IPC: G06F17/50 ,  G06F8/35

    Abstract: A method for automatically determining models signals of an FPGA program which are readable from the FPGA with the aid of a readback following an FPGA build, including the following steps: generating an FPGA model and generating an FPGA code from the FPGA model, the method comprising the additional step of an automatic analysis for the purpose of identifying signals which are readable from the FPGA with the aid of a readback, prior to the completion of the step of generating the FPGA code from the FPGA model, and the method comprises the step of outputting signals which are readable from the FPGA with the aid of a readback. A data processing device is also provided for carrying out the method.

    Method for troubleshooting the program logic of a system of distributed progammable gate arrays
    15.
    发明授权
    Method for troubleshooting the program logic of a system of distributed progammable gate arrays 有权

    公开(公告)号：US11017141B2

    公开(公告)日：2021-05-25

    申请号：US16874224

    申请日：2020-05-14

    Applicant: dSPACE digital signal processing and control engineering GmbH

    Inventor： Heiko Kalte ,  Dominik Lubeley ,  Marc Schlenger

    IPC: G06F30/38 ,  G06F30/34 ,  G06F115/02 ,  G06F117/02

    Abstract: A method for troubleshooting the program logic of a computer system. A first logic circuit and a first monitoring circuit, which is communicatively isolated from it, are programmed on a first programmable gate array of the computer system. A second logic circuit and a second monitoring circuit, which is communicatively isolated from it, are programmed on a second programmable gate array of the computer system. After an error has been detected in the program logic of the computer system, a first signal line, which applies a signal from the first logic circuit to a first signal input of the first monitoring circuit, is programmed in the first programmable gate array without changing the first logic circuit, and a second signal line, which applies a signal from the second logic circuit, is programmed in the second programmable gate array without changing the second logic circuit.

    Method for creating an FPGA netlist
    16.
    发明授权
    Method for creating an FPGA netlist 有权

    公开(公告)号：US10394989B2

    公开(公告)日：2019-08-27

    申请号：US15585335

    申请日：2017-05-03

    Applicant: dSPACE digital signal processing and control engineering GmbH

    Inventor： Heiko Kalte ,  Dominik Lubeley

    IPC: G06F17/50

    Abstract: A method for creating an FPGA netlist generated from an FPGA source code and at least one shadow register. The FPGA source code defines at least one function and at least one signal. The shadow register is assigned to the at least one signal, and is arranged and provided to store the value of the assigned signal at runtime. An option for reading out the stored signal value at runtime is provided. The function defined in the FPGA source code is not changed by the shadow register. The function described by the FPGA source code is executed by the FPGA, and a functional decoupling of the shadow register from the function described in the FPGA source code is provided. Via the decoupling, the shadow register maintains the signal value stored at the time of the decoupling while the function described in the FPGA source code is being executed.

    Method for determining the power consumption of a programmable logic device
    18.
    发明授权
    Method for determining the power consumption of a programmable logic device 有权

    公开(公告)号：US10102325B2

    公开(公告)日：2018-10-16

    申请号：US15291113

    申请日：2016-10-12

    Applicant: dSPACE digital signal processing and control engineering GmbH

    Inventor： Dominik Lubeley ,  Marc Schlenger ,  Heiko Kalte

    IPC: G06F17/00 ,  G06F17/50

    Abstract: A method for determining the power consumption of a programmable logic device, in which at least one configuration parameter is determined in accordance with a predefined configuration and at least one device parameter is determined in accordance with the programmable logic device. The predefined configuration is designed such that the programmable logic device exchanges data with a computing unit through at least one interface pin and receives data from at least one signal source and/or sends it to at least one signal receiver through at least one interface pin. At least one data characteristic of the data exchanged between the computing unit and the programmable logic device as well as at least one signal characteristic of the data received from the at least one signal source and/or sent to the at least one signal receiver are determined.

    Random access to signal values of an FPGA at runtime
    19.
    发明授权
    Random access to signal values of an FPGA at runtime 有权

    公开(公告)号：US10083043B2

    公开(公告)日：2018-09-25

    申请号：US14962359

    申请日：2015-12-08

    Applicant: dSPACE digital signal processing and control engineering GmbH

    Inventor： Heiko Kalte

    IPC: G06F17/50 ,  G06F9/4401

    CPC classification number: G06F9/4401 ,  G06F17/5027 ,  G06F17/5054

    Abstract: A method for accessing a signal value of an FPGA at runtime, including the steps of loading an FPGA hardware configuration into the FPGA, executing the FPGA hardware configuration in the FPGA, requesting a signal value of the FPGA, sending status data from a functional level of the FPGA to a configuration memory in its configuration level, reading the status data from the configuration memory as readback data, and determining the signal value of the readback data. A method is also provided for making an FPGA build, based on an FPGA model, using a hardware description language, including the steps of creating an FPGA hardware configuration, identifying memory locations of a configuration memory for status data of at least one signal value based on the FPGA hardware configuration, and creating a list with signal values accessible at runtime and the memory locations corresponding thereto.

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