公开(公告)号：US06484255B1

公开(公告)日：2002-11-19

申请号：US09399612

申请日：1999-09-20

申请人： Carole Dulong

发明人： Carole Dulong

IPC分类号： G06F9315

CPC分类号： G06F9/30018 ,  G06F9/30036 ,  G06F9/30072 ,  G06F9/30094

摘要： A method and apparatus for selectively writing data elements from packed data based upon a mask using predication. In one embodiment of the invention, for each data element of a packed data operand, the following is performed in parallel processing units: determining a predicate value for the data element from one or more bits of a corresponding packed data mask element indicating whether the data element is selected for writing to a corresponding storage location, and storing in the corresponding storage location the data element based on the predicate value.

摘要翻译： 一种用于基于使用预测的掩码来选择性地从打包数据写入数据元素的方法和装置。 在本发明的一个实施例中，对于打包数据操作数的每个数据元素，以并行处理单元执行以下操作：从对应的打包数据掩码元素的一个或多个位确定数据元素的谓词值，指示数据是否 元素被选择用于写入对应的存储位置，并且基于谓词值在相应的存储位置存储数据元素。

公开(公告)号：US06477641B2

公开(公告)日：2002-11-05

申请号：US09846752

申请日：2001-05-01

申请人： Alan L. Davis ,  Jonathan F. Humphreys ,  Todd M. Snider ,  Raj Kanagasabai

发明人： Alan L. Davis ,  Jonathan F. Humphreys ,  Todd M. Snider ,  Raj Kanagasabai

IPC分类号： G06F9315

CPC分类号： G06F8/44 ,  G06F8/52

摘要： An interactive translation system (10) includes a front end (40), a back end (42), and a user interface (16). The front end (40) is operable to identify source elements (86) in a source file (24). The back end (42) is operable to generate a translation file having translation elements corresponding to translation of said identified source elements (86) and having an interface (16) for receiving inputs for modifying said translation.

摘要翻译： 交互式翻译系统（10）包括前端（40），后端（42）和用户界面（16）。 前端（40）可操作以识别源文件（24）中的源元素（86）。 后端（42）可操作以产生具有对应于所述识别的源元件（86）的翻译并具有用于接收用于修改所述翻译的输入的接口（16）的翻译元素的翻译文件。

公开(公告)号：US06381690B1

公开(公告)日：2002-04-30

申请号：US08509867

申请日：1995-08-01

申请人： Ruby B. Lee

发明人： Ruby B. Lee

IPC分类号： G06F9315

CPC分类号： G06F7/762 ,  G06F7/76 ,  G06F9/30032 ,  G06F9/30036

摘要： An apparatus for operating on the contents of an input register to generate the contents of an output register which contains a permutation, with or without repetitions, or a combination of the contents of the input register. The apparatus partitions the input register into a plurality of sub-words, each sub-word being characterized by a location in the input register and a length greater than one bit. In response to an instruction specifying a rearrangement of the input register, the present invention directs at least one of the sub-words in the input register to a location in the output register that differs from the location occupied by the sub-word in the input register. The ordering of the sub-words in the output register differ from the order obtainable by a single shift instruction. In the preferred embodiment of the present invention, the invention is implemented by modifying a conventional shifter comprising a plurality of layers of multiplexers. The modification comprises independently setting the control signals for at least one of the multiplexers in at least one of the layers.

摘要翻译： 一种用于对输入寄存器的内容进行操作以产生包含有或没有重复的排列或输入寄存器的内容的组合的输出寄存器的内容的装置。 该设备将输入寄存器分割为多个子字，每个子字的特征在于输入寄存器中的一个位置，长度大于一位。 响应于指定输入寄存器的重排的指令，本发明将输入寄存器中的至少一个子字引导到输出寄存器中与输入中的子字占据的位置不同的位置 寄存器。 输出寄存器中的子字的排序与通过单个移位指令可获得的顺序不同。 在本发明的优选实施例中，本发明通过修改包括多层复用器的常规移位器来实现。 修改包括独立地设置至少一个层中的多路复用器中的至少一个的控制信号。

公开(公告)号：US06332188B1

公开(公告)日：2001-12-18

申请号：US09187479

申请日：1998-11-06

申请人： Douglas Garde ,  Alexei Zatsman ,  Aryeh Lezerovitz ,  Zvi Greenfield ,  David R. Levine ,  Jose Fridman

发明人： Douglas Garde ,  Alexei Zatsman ,  Aryeh Lezerovitz ,  Zvi Greenfield ,  David R. Levine ,  Jose Fridman

IPC分类号： G06F9315

CPC分类号： G06F9/30018 ,  G06F9/30 ,  G06F9/30032 ,  G06F9/30101

摘要： A digital signal processor includes a computation block with an arithmetic logic unit, a multiplier, a shifter and a register file. The computation block includes a plurality of registers for storing instructions and operands in a bit format as a continuous bit stream, and utilizes a bit transfer mechanism for transferring in a single cycle a bit field of an arbitrary bit length between the plurality of registers and the shifter. The plurality of registers may be general purpose registers located in the register file. The register file may further include at least one control information register for storing control information used by the bit transfer mechanism.

摘要翻译： 数字信号处理器包括具有算术逻辑单元，乘法器，移位器和寄存器文件的计算块。 计算块包括用于以位格式存储指令和操作数作为连续比特流的多个寄存器，并且利用比特传送机制在单个周期内传送多个寄存器之间的任意比特长度的比特字段和 移位器 多个寄存器可以是位于寄存器文件中的通用寄存器。 寄存器文件还可以包括至少一个控制信息寄存器，用于存储比特传送机制使用的控制信息。

公开(公告)号：US06728870B1

公开(公告)日：2004-04-27

申请号：US09680894

申请日：2000-10-06

申请人： Charles P. Roth ,  Ravi P. Singh ,  Gregory A. Overkamp ,  Ryo Inoue

发明人： Charles P. Roth ,  Ravi P. Singh ,  Gregory A. Overkamp ,  Ryo Inoue

IPC分类号： G06F9315

CPC分类号： G06F9/30032 ,  G06F9/3013

摘要： In one embodiment, a programmable processor is adapted to conditionally move data between a pointer register and a data register in response to a single machine instruction. The processor has a plurality of pipelines. In response to the machine instruction, a control unit directs the pipelines to forward the data across the pipelines in order to move the data between the registers.

摘要翻译： 在一个实施例中，可编程处理器适于响应于单个机器指令在指针寄存器和数据寄存器之间有条件地移动数据。 处理器具有多个管道。 响应于机器指令，控制单元引导管线通过管线转发数据，以便在寄存器之间移动数据。

公开(公告)号：US06654872B1

公开(公告)日：2003-11-25

申请号：US09490888

申请日：2000-01-27

申请人： T. R. Ramesh ,  Korbin S. Van Dyke

发明人： T. R. Ramesh ,  Korbin S. Van Dyke

IPC分类号： G06F9315

CPC分类号： G06F9/3816 ,  G06F9/30149

摘要： An instruction aligner and method evaluates a fixed length instruction cache line by breaking it into at least two components. These two components, in one embodiment, include half of the instruction cache line being designated as most significant bytes and the second half of the instruction cache line being designated as least significant bytes. A byte right rotator is responsible for feeding the next sixteen bytes of the instruction stream, while a byte right shifter shifts the unused bytes of the current sixteen bytes the aligner is working on. The byte rotator and byte shifter combine to provide aligned variable length instructions for decoding based on either a fetch PC value or current instruction length.

摘要翻译： 指令对齐器和方法通过将固定长度的指令高速缓存行分解成至少两个组件来评估它。 在一个实施例中，这两个组件包括指定高速缓存行的一半被指定为最高有效字节，指令高速缓存行的后半部分被指定为最低有效字节。 一个字节右旋转器负责馈送指令流的下一个十六个字节，而一个字节右移位器移位对准器正在工作的当前十六个字节的未使用字节。 字节转换器和字节移位器组合以提供对准的可变长度指令，用于基于获取的PC值或当前指令长度进行解码。

公开(公告)号：US06516406B1

公开(公告)日：2003-02-04

申请号：US09657448

申请日：2000-09-08

申请人： Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan

发明人： Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan

IPC分类号： G06F9315

CPC分类号： G06F9/30036 ,  G06F7/49921 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30192 ,  G06F9/30196

摘要： An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.

摘要翻译： 一种装置包括指令解码器，第一和第二源寄存器以及耦合到解码器的电路，用于从源寄存器接收压缩数据，并根据解码器接收到的解包指令对打包数据进行解包。 从第一源寄存器接收第一打包数据元素和第三打包数据元素。 从第二源寄存器接收第二打包数据元素和第四打包数据元素。 所述电路将打包的数据元素复制到目的地寄存器中，其中与第一打包数据元素相邻的第二打包数据元素，与第二打包数据元素相邻的第三打包数据元素以及与第三打包数据元素相邻的第四打包数据元素 数据元素。

公开(公告)号：US06446198B1

公开(公告)日：2002-09-03

申请号：US09409669

申请日：1999-09-30

申请人： Ali Sazegari

发明人： Ali Sazegari

IPC分类号： G06F9315

CPC分类号： G06F7/764 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/345 ,  G06F17/30952

摘要： A lookup operation is carried out on a data table by logically dividing the data table into a number of smaller sets of data that can be indexed with a single byte of data. Each set of data consists of two vectors, which constitute the operands for a permute instruction. Only a limited number of bits are required to index into the table during the execution of this instruction. The remaining bits of each index are used as masks into a series of select instructions. The select instruction chooses between two vector components, based on the mask, and places the selected components into a new vector. The mask is generated by shifting one of the higher order bits of the index to the most significant position, and then propagating that bit throughout a byte, for example by means of an arithmetic shift. This procedure is carried out for all of the index bytes in the vector, to generate a select mask. The select mask is then used during a select operation, to choose between the results of permute instructions on different ones of the logically divided sets of data. Multi-byte table entries are retrieved by replicating each index value and adding consecutive values to form multiple consecutive index values that are then used in multiple permute operations.

公开(公告)号：US06263401B1

公开(公告)日：2001-07-17

申请号：US08940834

申请日：1997-09-30

申请人： Jonathan K. Ross ,  Cary A. Coutant ,  Carol L. Thompson ,  Achmed R. Zahir

发明人： Jonathan K. Ross ,  Cary A. Coutant ,  Carol L. Thompson ,  Achmed R. Zahir

IPC分类号： G06F9315

CPC分类号： G06F9/463 ,  G06F9/30105 ,  G06F9/30127 ,  G06F9/30134

摘要： A computer-implemented method and apparatus for transferring the contents of a general register, in a register stack, to a location in a backing store in a main memory are described. When transferring the contents of a general register to a location in the backing store, the invention proposes collecting attribute bits included in each general register of a predetermined group of registers in a temporary collection register. Once the temporary collection register has been filled, the contents of this register are written to the next available location in the backing store. Similarly, on the restoration of registers from the backing store, a collection of attribute bits saved in the backing register is transferred to a temporary collection register. Thereafter, each attribute bit is saved together with associated data into a general register, thereby to restore the former contents of each general register.

摘要翻译： 描述了一种用于将寄存器堆栈中的通用寄存器的内容传送到主存储器中的后备存储器中的位置的计算机实现的方法和装置。 当将通用寄存器的内容传送到后备存储器中的位置时，本发明提出收集临时收集寄存器中预定寄存器组的每个通用寄存器中包含的属性位。 一旦临时收集寄存器被填写，该寄存器的内容将被写入后备存储中的下一个可用位置。 类似地，在从后台存储器恢复寄存器时，保存在后备寄存器中的属性位的集合被传送到临时收集寄存器。 此后，每个属性位与相关联的数据一起保存到通用寄存器中，从而恢复每个通用寄存器的前一个内容。