公开(公告)号：US06820195B1

公开(公告)日：2004-11-16

申请号：US09410545

申请日：1999-10-01

申请人： David E. Shepherd

发明人： David E. Shepherd

IPC分类号： G06F9315

CPC分类号： G06F9/30043 ,  G06F9/30032 ,  G06F9/3816 ,  G06F9/383

摘要： Embodiments of the present invention are directed to an architecture structured to handle unaligned memory references. In one embodiment, a method for loading unaligned data stored in a plurality of memory locations comprises loading a first part of the unaligned data into a first storage location; rotating and sign-extending the first part of the unaligned data in the first storage location from a first position to a second position; loading a second part of the unaligned data into a second storage location; rotating the second part of the unaligned data in the second storage location from a third position to a fourth position; and combining the first storage location with the second location using a logical operation into a result storage location.

摘要翻译： 本发明的实施例涉及一种结构化以处理未对齐的存储器引用的架构。 在一个实施例中，用于加载存储在多个存储器位置中的未对齐数据的方法包括将未对齐数据的第一部分加载到第一存储位置中; 将第一存储位置中的未对齐数据的第一部分从第一位置旋转并签名延伸到第二位置; 将未对齐数据的第二部分加载到第二存储位置; 将第二存储位置中的未对齐数据的第二部分从第三位置旋转到第四位置; 以及使用逻辑操作将所述第一存储位置与所述第二位置组合到结果存储位置。

公开(公告)号：US06442674B1

公开(公告)日：2002-08-27

申请号：US09223297

申请日：1998-12-30

申请人： Chan Lee ,  Hitesh Ahuja ,  Robert F. Krick

发明人： Chan Lee ,  Hitesh Ahuja ,  Robert F. Krick

IPC分类号： G06F9315

CPC分类号： G06F9/3814 ,  G06F9/3802 ,  G06F9/3808

摘要： A method and system for reducing a latency of microprocessor instructions in transit along an instruction pipeline of a microprocessor by bypassing, at certain times, a fill buffer located between an instruction source and a trace cache unit on the instruction pipeline. The signal path through the fill buffer to the trace cache unit represent a first signal path. In the instruction pipeline, a second signal path is also provided, one which also leads instructions to the trace cache unit, not through the fill buffer, but through a latch provided on the second instruction path. If the latch is enabled, a set of instructions appearing at the input of the fill buffer is transmitted through the latch along the second instruction path and to the trace cache. As a result, the fill buffer is bypassed and a reduced latency for the bypassed instructions is achieved along the instruction pipeline.

摘要翻译： 一种方法和系统，用于通过在特定时间绕过位于指令流水线上的指令源和跟踪高速缓存单元之间的填充缓冲器来减少沿着微处理器的指令流水线传送的微处理器指令的等待时间。 通过填充缓冲器到跟踪缓存单元的信号路径表示第一信号路径。 在指令流水线中，还提供第二信号路径，其中一个信号路径也不通过填充缓冲器，而是经由设置在第二指令路径上的锁存器将指令引导到跟踪高速缓存单元。 如果锁存器被使能，则出现在填充缓冲器的输入端的一组指令沿着第二指令路径通过锁存器传送到跟踪缓存。 结果，溢出缓冲器被旁路，并且沿着指令流水线实现了绕过指令的降低的等待时间。

公开(公告)号：US06754810B2

公开(公告)日：2004-06-22

申请号：US10120538

申请日：2002-04-10

申请人： Timothy A. Elliott ,  G. Glenn Henry

发明人： Timothy A. Elliott ,  G. Glenn Henry

IPC分类号： G06F9315

CPC分类号： G06F9/30014 ,  G06F9/30025

摘要： An apparatus and method for bi-directional format conversion and transfer of data between integer and floating point registers is provided. A floating point register is configured to store floating point data, and integer data, in a variety of numerical formats. Data is moved in and out of the floating point register as integer data, and is converted into floating point format as needed. Separate processor instructions are provided for format conversion and data transfer to allow conversion and transfer operations to be separated.

摘要翻译： 提供了一种用于在整数和浮点寄存器之间双向格式转换和数据传输的装置和方法。 浮点寄存器被配置为以各种数字格式存储浮点数据和整数数据。 数据作为整数数据移入和移出浮点寄存器，并根据需要转换为浮点格式。 提供单独的处理器指令用于格式转换和数据传输，以允许转换和传输操作分离。

公开(公告)号：US06643718B1

公开(公告)日：2003-11-04

申请号：US09621070

申请日：2000-07-21

申请人： Chao-Yu Chen ,  Hui-Neng Chang ,  Sui-His Chu

发明人： Chao-Yu Chen ,  Hui-Neng Chang ,  Sui-His Chu

IPC分类号： G06F9315

CPC分类号： G06F7/00 ,  G06F9/52 ,  G06F9/522

摘要： A barrier control scheme controls the order dependency of items in a multiple FIFO queue structure. The barrier control scheme includes a cycle ID generator, a barrier bit/barrier ID generator and a cycle ID and barrier ID comparator. Each incoming item to the FIFOs is assigned a cycle ID. If an incoming item of a first FIFO has order dependency on items of a second FIFO, a barrier bit is set and a barrier ID is determined and generated by the barrier bit/barrier ID generator. The barrier bit and barrier ID are inserted in the first FIFO along with other fields of the incoming item. When an item is to be consumed, the cycle ID and barrier ID comparator compares its barrier ID and the cycle IDs of items in the second FIFO. The item to be consumed is blocked until all items on which the item is dependent are consumed in the second FIFO.

摘要翻译： 障碍控制方案控制多FIFO队列结构中项目的顺序依赖性。 屏障控制方案包括循环ID发生器，屏障位/屏障ID发生器和周期ID和屏障ID比较器。 每个进入FIFO的输入项都被分配一个循环ID。 如果第一FIFO的输入项目具有与第二FIFO的项目有顺序依赖关系，则设置障碍位并且屏障ID /屏障ID发生器确定并产生屏障ID。 屏障位和屏障ID与输入项目的其他字段一起插入第一个FIFO。 当一个物品被消耗时，循环ID和屏障ID比较器比较其屏障ID和第二个FIFO中项目的循环ID。 要消费的项目被阻止，直到所有项目依赖的项目在第二个FIFO中被消耗。

公开(公告)号：US06260137B1

公开(公告)日：2001-07-10

申请号：US08928764

申请日：1997-09-12

申请人： Rod G. Fleck ,  Daniel Martin

发明人： Rod G. Fleck ,  Daniel Martin

IPC分类号： G06F9315

CPC分类号： G06T1/60 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30112 ,  G06F9/345 ,  G06F9/3816

摘要： The present invention relates to a data processing unit comprising a register file, a register load and store buffer connected to the register file, a single memory, and a bus having at least first and second word lines to form a double word wide bus coupling the register load and store buffer with said single memory. The register file at least two sets of registers whereby the first set of registers can be coupled with one of the word lines and the second set of registers can be coupled with the respective other word lines, a load and store control unit for transferring data from or to the memory.

摘要翻译： 数据处理单元技术领域本发明涉及一种数据处理单元，包括寄存器文件，连接到寄存器文件的寄存器加载和存储缓冲器，单个存储器和具有至少第一和第二字线的总线，以形成双字宽总线， 使用所述单个存储器注册加载和存储缓冲区。 寄存器文件至少两组寄存器，其中第一组寄存器可以与字线和第二组寄存器耦合，可以与相应的其他字线耦合，一个负载和存储控制单元，用于从 或记忆。

公开(公告)号：US06671797B1

公开(公告)日：2003-12-30

申请号：US09702463

申请日：2000-10-31

申请人： Jeremiah E. Golston

发明人： Jeremiah E. Golston

IPC分类号： G06F9315

CPC分类号： G06F9/30018 ,  G06F9/30036

摘要： A data processing system is provided with a digital signal processor which has an instruction for expanding one bit to form a mask field. In one form of the instruction, a first bit from a two-bit mask in a source operand is replicated and placed in an least significant half word of a destination operand while a second bit from the two-bit mask in the source operand is replicated and placed in a most significant half word of the destination operand. In another form of the instruction, a first bit from a four bit mask in a source operand is replicated and placed in a least significant byte of a destination operand, a second bit from the four-bit mask in the source operand is replicated and placed in a second least significant byte of the destination operand, a third bit from the four-bit mask is replicated and placed in a second most significant byte of the destination operand and a fourth bit form the four-bit mask is replicated and placed in a most significant byte of the destination operand.

摘要翻译： 数据处理系统具有数字信号处理器，该数字信号处理器具有用于扩展一位以形成掩模场的指令。 在指令的一种形式中，源操作数中的二位掩码的第一位被复制并放置在目标操作数的最低有效半字中，而源操作数中的二位掩码的第二位被复制 并放置在目标操作数的最高半字中。 在指令的另一种形式中，源操作数中的四位掩码的第一位被复制并放置在目标操作数的最低有效字节中，源操作数中的四位掩码的第二位被复制和放置 在目的地操作数的第二个最低有效字节中，来自四位掩码的第三位被复制并放置在目标操作数的第二个最高有效字节中，并且四位掩码被复制并放置在第四位中 目标操作数的最高有效字节。

公开(公告)号：US06594754B1

公开(公告)日：2003-07-15

申请号：US09348404

申请日：1999-07-07

申请人： Stephan J. Jourdan ,  Gad S. Sheaffer ,  Ronny Ronen

发明人： Stephan J. Jourdan ,  Gad S. Sheaffer ,  Ronny Ronen

IPC分类号： G06F9315

CPC分类号： G06F9/3857 ,  G06F9/30032 ,  G06F9/30167 ,  G06F9/384

摘要： A computer architecture to process move instructions by allowing multiple mappings between logical registers and the same physical register. In one embodiment, a counter is associated with each physical register to indicate when the physical register is free. A register-to-register move instruction is processed by mapping the logical destination register of the move instruction to the same physical register to which the logical source register of the move instruction is mapped. An immediate-to-register move instruction is processed by mapping the logical destination register of the move instruction to a physical register storing the immediate.

摘要翻译： 通过允许逻辑寄存器和同一物理寄存器之间的多个映射来处理移动指令的计算机体系结构。 在一个实施例中，计数器与每个物理寄存器相关联，以指示何时物理寄存器是空闲的。 通过将移动指令的逻辑目标寄存器映射到映射了移动指令的逻辑源寄存器的同一物理寄存器来处理寄存器到寄存器移动指令。 通过将移动指令的逻辑目标寄存器映射到存储立即数的物理寄存器来处理立即注册移动指令。

公开(公告)号：US06591357B2

公开(公告)日：2003-07-08

申请号：US09795672

申请日：2001-02-26

申请人： Ethan A. Mirsky

发明人： Ethan A. Mirsky

IPC分类号： G06F9315

CPC分类号： G06F7/57 ,  G06F7/49921 ,  G06F7/505 ,  G06F7/544 ,  G06F2207/3828

摘要： A method and an apparatus for configuring arbitrary sized data paths comprising multiple context processing elements (MCPEs) are provided. Multiple MCPEs may be chained to form wider-word data paths of arbitrary widths, wherein a first ALU serves as the most significant byte (MSB) of the data path while a second ALU serves as the least significant byte (LSB) of the data path. The ALUs of the data path are coupled using a left-going, or forward, carry chain for transmitting at least one carry bit from the LSB ALU to the MSB ALU. The MSB ALU comprises configurable logic for generating at least one signal in response to a carry bit received over the left-going carry chain, the at least one signal comprising a saturation signal and a saturation value. The MCPEs of the data path use configurable logic to manipulate a resident bit sequence in response to the saturation signal transmitted thereby reconfiguring, or changing the operation of, the data path in response to he saturation signal. The carry chains support carry operations for non-local functions comprising minimum and maximum arithmetic operations.

摘要翻译： 提供了一种用于配置包括多个上下文处理元件（MCPE）的任意大小的数据路径的方法和装置。 多个MCPE可以链接以形成任意宽度的更宽字数据路径，其中第一ALU用作数据路径的最高有效字节（MSB），而第二ALU用作数据路径的最低有效字节（LSB） 。 数据路径的ALU使用向左或向前的进位链进行耦合，用于将至少一个进位位从LSB ALU发送到MSB ALU。 MSB ALU包括可配置逻辑，用于响应于通过左路进位链接收的进位位产生至少一个信号，所述至少一个信号包括饱和信号和饱和度值。 数据路径的MCPE使用可配置逻辑来响应传输的饱和信号来操纵驻留比特序列，从而根据饱和信号重新配置或改变数据路径的操作。 进位链支持对包括最小和最大算术运算的非局部函数进行操作。

公开(公告)号：US06523108B1

公开(公告)日：2003-02-18

申请号：US09448568

申请日：1999-11-23

申请人： David James ,  Jung-Jen Liu

发明人： David James ,  Jung-Jen Liu

IPC分类号： G06F9315

CPC分类号： G06F9/30029 ,  G06F9/30032

摘要： Deposit and extract instructions include an opcode, a source address, a destination address, a shift number, and a K-bit mask string. The opcode describes the operations to be performed upon a J-bit source string and an N-bit destination string. The source address points to the memory location of the J-bit source string. The destination address points to the memory location of the N-bit destination string. The shift number indicates the number of bits the J-bit source string is to be shifted to generate a shifted bit string. The combination of the shifted bit string with the N-bit destination string is conducted under the control of the K-bit mask string. The invention is useful for high speed digital data processing, such as that performed by devices operating under the IEEE 1394 protocol.

摘要翻译： 存储和提取指令包括操作码，源地址，目的地址，移位号和K位掩码字符串。 操作码描述了要在J位源字符串和N位目的字符串上执行的操作。 源地址指向J位源字符串的存储位置。 目标地址指向N位目的地字符串的存储单元。 移位数表示J位源字符串要移位以产生移位的位串的位数。 移位的位串与N位目的地串的组合在K位掩码串的控制下进行。 本发明对于诸如由根据IEEE 1394协议操作的设备执行的高速数字数据处理是有用的。

公开(公告)号：US06718456B1

公开(公告)日：2004-04-06

申请号：US09587177

申请日：2000-06-02

申请人： Michael Ott

发明人： Michael Ott

IPC分类号： G06F9315

CPC分类号： G06F9/30032 ,  G06F5/01 ,  G06F9/30025 ,  G06F9/30036

摘要： Disclosed herein is a apparatus and method for packing a 16-bit number into an 8-bit result byte. The method and apparatus utilize a parallel processing right shift circuit and a filter to obtain desired results. The parallel processes are comprised of a plurality of multiplexers capable of discretely analyzing smaller groups of bits. In this manner, higher throughput may be obtained than previously known.

摘要翻译： 这里公开了一种用于将16位数字打包成8位结果字节的装置和方法。 该方法和装置利用并行处理右移电路和滤波器来获得期望的结果。 并行处理由能够离散分析较小比特组的多个多路复用器组成。 以这种方式，可以获得比先前已知的更高的生产量。