公开(公告)号：US10885994B2

公开(公告)日：2021-01-05

申请号：US16828477

申请日：2020-03-24

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Huai-Yuan Tseng ,  Deepanshu Dutta

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/04 ,  H01L27/1157 ,  G11C11/56 ,  H01L27/11524

Abstract: A circuit includes a program controller configured to perform a program operation with interleaved program-verify loops to program memory cells in a same block. During each program-verify loop, a control gate line voltage supply circuit first supplies a program pulse to a first cell of the block and then, before verifying the first cell, supplies a program pulse to a second cell of the block. After the program pulses are sent, the control gate line supply circuit consecutively supplies verify pulses to the first cell and the second cell such that a delay is introduced between the respective program and verify stages of the first and second cells. Additionally, a constant voltage bias on common control gate lines of the first and second memory cells is applied during the consecutive verify stages. Further, an order of verify pulses may be applied in a reverse order during a verify stage.

公开(公告)号：US10861571B1

公开(公告)日：2020-12-08

申请号：US16432000

申请日：2019-06-05

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Yu-chung Lien

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C11/56

Abstract: A methodology and structure for performing an erase verify in non-volatile memory is described. Both the odd wordlines and the even wordlines are driven to a high voltage level. This can be done simultaneously. The simultaneous charging of both the odd wordlines and the even wordlines, even when the erase verify will occur on only one of the odd or even wordlines reduces RC delay in the charging of the wordlines. After the odd and even wordlines are charged, then one set of wordlines, either the odd or even wordlines, is dropped to the erase verify voltage. The erase sense operation is then performed.

公开(公告)号：US10832778B1

公开(公告)日：2020-11-10

申请号：US16455872

申请日：2019-06-28

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Huai-yuan Tseng ,  Deepanshu Dutta

IPC: G11C16/08 ,  G11C16/24 ,  G11C16/04

Abstract: A methodology and structure for driving a selected wordline to a negative voltage without the need for a negative wordline voltage generator. The methodology includes the step of boosting a non-selected wordline to a first positive voltage. The methodology proceeds with holding a selected wordline, which is adjacent to and capacitively coupled with the non-selected wordline, at zero voltage. The methodology continues with floating the selected wordline. The methodology proceeds with driving the non-selected wordline to a lower voltage to shift the selected wordline to less than zero volts due to capacitance effects. The methodology continues with the step of accelerating charge loss in a defective memory cell connected to the selected wordline while at a negative voltage during a soft erase operation.

公开(公告)号：US10741257B1

公开(公告)日：2020-08-11

申请号：US16453291

申请日：2019-06-26

Applicant: SanDisk Technologies LLC

Inventor： Jianzhi Wu ,  Xiang Yang

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/34 ,  G11C16/24

Abstract: A method and system are provided for reading a non-transitory memory array. When a default read operation is performed and has failed, a dynamic sensing bit line voltage (VBLC) enhanced read or a dynamic sense time read is performed. According to the dynamic VBLC enhanced read or the dynamic sense time enhanced read, the VBLC or the sense time is increased, and a read is performed with the increased VBLC or increased sense time. If this enhanced read is unsuccessful, and if a maximum VBLC or a maximum sense time has not yet been reached, the VBLC or the sense time is increased again, and another read is performed. Once the maximum VBLC or a maximum sense time has been reached, if the read is still not successful, a read failure is reported.

公开(公告)号：US20200227125A1

公开(公告)日：2020-07-16

申请号：US16829692

申请日：2020-03-25

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Deepanshu Dutta ,  Gerrit Jan Hemink ,  Tai-Yuan Tseng ,  Yan Li

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/24 ,  G11C16/04 ,  G11C11/56

Abstract: An apparatus includes a programming circuit configured to supply a program pulse to increase a threshold voltage of a memory cell. The apparatus also includes a sensing circuit configured to determine that the threshold voltage of the memory cell satisfies a trigger threshold voltage in response to the program pulse. The apparatus further includes a damping circuit configured to increase a voltage of a bit line connected to the memory cell after initiation of and during a second program pulse in response to the threshold voltage of the memory cell satisfying the trigger threshold voltage, the second program pulse being sent by the programming circuit.

公开(公告)号：US20200227124A1

公开(公告)日：2020-07-16

申请号：US16828477

申请日：2020-03-24

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Huai-Yuan Tseng ,  Deepanshu Dutta

IPC: G11C16/34 ,  G11C16/10

Abstract: A circuit includes a program controller configured to perform a program operation with interleaved program-verify loops to program memory cells in a same block. During each program-verify loop, a control gate line voltage supply circuit first supplies a program pulse to a first cell of the block and then, before verifying the first cell, supplies a program pulse to a second cell of the block. After the program pulses are sent, the control gate line supply circuit consecutively supplies verify pulses to the first cell and the second cell such that a delay is introduced between the respective program and verify stages of the first and second cells. Additionally, a constant voltage bias on common control gate lines of the first and second memory cells is applied during the consecutive verify stages. Further, an order of verify pulses may be applied in a reverse order during a verify stage.

公开(公告)号：US20200066363A1

公开(公告)日：2020-02-27

申请号：US16145012

申请日：2018-09-27

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/32 ,  G11C16/04

Abstract: An apparatus includes a programming circuit configured to deliver a series of program loops to a memory cell. The apparatus further includes a sensing circuit configured to sense an electrical characteristic of the memory cell for a sensing time during each program loop. The apparatus also includes an alteration circuit configured to alter the sensing time of a subsequent program loop in response to a programming condition.

公开(公告)号：US10573395B1

公开(公告)日：2020-02-25

申请号：US16206718

申请日：2018-11-30

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Gerrit Jan Hemink

IPC: G11C16/28 ,  G11C16/04 ,  G11C16/08 ,  G11C11/56 ,  G11C16/34 ,  H01L27/1157

Abstract: Non-volatile memory strings, which are coupled to respective bit lines and source lines, may include multiple non-volatile memory cells coupled to respective word lines. Multiple sensing operations may be used to determine data programmed into a particular non-volatile memory cell. For example, a control circuit may sense multiple values from a particular non-volatile memory cell included in a non-volatile memory string using different voltage levels on a source line coupled to the non-volatile memory string. The control circuit may select one of the multiple values based on a program state of a different non-volatile memory cell adjacent to the particular non-volatile memory cell.

公开(公告)号：US10559368B1

公开(公告)日：2020-02-11

申请号：US16056838

申请日：2018-08-07

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang

IPC: G11C16/34 ,  G11C5/02 ,  G11C7/12 ,  H01L27/11 ,  G11C8/08 ,  G11C16/10 ,  G11C16/28 ,  H01L27/11582 ,  H01L27/1157 ,  G11C16/04 ,  H01L27/11524 ,  H01L27/11556

Abstract: Program disturb is a condition that includes the unintended programming while performing a programming process for memory cells, where the program disturb can affect both memory cells and select gates in a NAND structure. During a pre-charge phase of a programming operation, a drain side select gate may be biased to a higher voltage than an adjacent word line, resulting in a disturb of the select gate due to hot-electron injection. This can raise the threshold voltage of the select gate, causing error in reading the NAND string or even making it inaccessible. To help avoid this problem, during a program pre-charge, the voltage applied to the select gate is raised in a sequence of steps, rather than driving the select gate directly to its final pre-charge voltage level.

公开(公告)号：US10535412B2

公开(公告)日：2020-01-14

申请号：US15963647

申请日：2018-04-26

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Huai-Yuan Tseng ,  Deepanshu Dutta ,  Jianzhi Wu ,  Gerrit Jan Hemink

IPC: G11C16/06 ,  G11C16/34 ,  G11C16/24 ,  G11C16/26 ,  G11C16/10

Abstract: A memory device includes memory cells coupled to a word line. The memory device includes a controller coupled to the word line. The controller is configured to program the memory cells coupled to the word line. The controller is configured to verify a programmed status of a first subset of the memory cells coupled to the word line and a programmed status of a second subset of the memory cells coupled to the word line, based on the programmed status of the first subset of the memory cells.