公开(公告)号：US20150044875A1

公开(公告)日：2015-02-12

申请号：US13963631

申请日：2013-08-09

Applicant: United Microelectronics Corp.

Inventor： Yu-Cheng Tung

IPC: H01L21/308 ,  H01L21/033 ,  G03F1/68

CPC classification number: G03F1/68 ,  G03F1/70 ,  G03F7/70458 ,  H01L21/0337

Abstract: A method of forming a pattern is disclosed. First, N kinds of different photomask patterns are provided. Thereafter, the N kinds of different photomask patterns are transferred to a hard mask layer by using at least N−1 kinds of light sources with different wavelengths, so as to form a hard mask pattern, wherein one of the at least N−1 kinds of light sources with different wavelengths is a light source with a wavelength of 193 nm, and N is an integer of three or more.

Abstract translation: 公开了形成图案的方法。 首先，提供N种不同的光掩模图案。 此后，通过使用至少具有不同波长的N-1种光源将N种不同的光掩模图案转印到硬掩模层，以形成硬掩模图案，其中至少N-1种之一 不同波长的光源是波长193nm的光源，N是3以上的整数。

公开(公告)号：US08930860B2

公开(公告)日：2015-01-06

申请号：US14231999

申请日：2014-04-01

Applicant: United Microelectronics Corp.

Inventor： Yu-Cheng Tung

IPC: G06F17/50 ,  H01L21/033 ,  G03F7/20

CPC classification number: H01L21/0337 ,  G03F1/70 ,  G03F7/203 ,  G06F17/5045 ,  G06F17/5072 ,  G06F17/5081

Abstract: A layout decomposition method and a method for manufacturing a semiconductor device applying the same are provided. According to the layout decomposition method, a design layout is received by the logic processor of a computing system. A design rule for layout decomposition is then identified by the logic processor, including identifying dense areas (areas with densely distributed features) on a substrate, and identifying areas with odd-numbered features on the substrate. Next, a first mask with a first pattern and a second mask with a second pattern are generated corresponding to results of design rule identification by the computing system for fabricating patterns of features in at least two of the areas with odd-numbered features in one of the dense areas.

Abstract translation: 提供了布局分解方法和制造应用其的半导体器件的方法。 根据布局分解方法，计算系统的逻辑处理器接收到设计布局。 然后由逻辑处理器识别用于布局分解的设计规则，包括识别基板上的密集区域（具有密集分布的特征的区域），以及识别基板上具有奇数特征的区域。 接下来，对应于用于在具有奇数特征的至少两个区域中的特征的制造图案的计算系统的设计规则识别的结果对应地生成具有第一图案的第一掩模和具有第二图案的第二掩模 密集的地区。

公开(公告)号：US20140213066A1

公开(公告)日：2014-07-31

申请号：US14231999

申请日：2014-04-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Tung

IPC: H01L21/033 ,  G06F17/50

CPC classification number: H01L21/0337 ,  G03F1/70 ,  G03F7/203 ,  G06F17/5045 ,  G06F17/5072 ,  G06F17/5081

Abstract: A layout decomposition method and a method for manufacturing a semiconductor device applying the same are provided. According to the layout decomposition method, a design layout is received by the logic processor of a computing system. A design rule for layout decomposition is then identified by the logic processor, including identifying dense areas (areas with densely distributed features) on a substrate, and identifying areas with odd-numbered features on the substrate. Next, a first mask with a first pattern and a second mask with a second pattern are generated corresponding to results of design rule identification by the computing system for fabricating patterns of features in at least two of the areas with odd-numbered features in one of the dense areas.

Abstract translation: 提供了布局分解方法和制造应用其的半导体器件的方法。 根据布局分解方法，由计算系统的逻辑处理器接收设计布局。 然后由逻辑处理器识别用于布局分解的设计规则，包括识别基板上的密集区域（具有密集分布的特征的区域），以及识别基板上具有奇数特征的区域。 接下来，对应于用于在具有奇数特征的至少两个区域中的特征的制造图案的计算系统的设计规则识别的结果对应地生成具有第一图案的第一掩模和具有第二图案的第二掩模 密集的地区。

公开(公告)号：US08739083B1

公开(公告)日：2014-05-27

申请号：US13676185

申请日：2012-11-14

Applicant: United Microelectronics Corp.

Inventor： Yu-Cheng Tung

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/70 ,  G06F17/5045 ,  G06F17/5072

Abstract: A layout decomposition method and a method for manufacturing a semiconductor device applying the same are provided. According to the layout decomposition method, a design layout is received by the logic processer of a computing system. A design rule for layout decomposition is then identified by the logic processer, including identifying the loose areas (areas with loosely distributed features) and dense areas (areas with densely distributed features) on a substrate, and identifying first areas with odd-numbered features and second areas with even-numbered features on the substrate. Next, a first mask with a first pattern and a second mask with a second pattern are generated corresponding to results of design rule identification by the computing system.

Abstract translation: 提供了布局分解方法和制造应用其的半导体器件的方法。 根据布局分解方法，计算系统的逻辑处理器接收到设计布局。 然后由逻辑处理器识别布局分解的设计规则，包括识别衬底上松散区域（具有松散分布特征的区域）和密集区域（具有密集分布特征的区域），以及识别具有奇数特征的第一区域，以及 在基板上具有偶数特征的第二区域。 接下来，对应于计算系统的设计规则识别的结果，产生具有第一图案的第一掩模和具有第二图案的第二掩模。

公开(公告)号：US20220122845A1

公开(公告)日：2022-04-21

申请号：US17561989

申请日：2021-12-26

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Yu-Cheng Tung ,  Fu-Che Lee

IPC: H01L21/033 ,  H01L27/108

Abstract: A semiconductor device includes a substrate and a material disposed on the substrate. The material layer includes plural first patterns arranged parallel and separately in an array within a first region of the substrate, and plural second patterns parallel and separately disposed at two opposite sides of the first patterns, and plural third patterns parallel and separately disposed at another two opposite sides of the first patterns, wherein each of the third patterns has a relative greater dimension than that of each of the first patterns.

公开(公告)号：US11264488B2

公开(公告)日：2022-03-01

申请号：US16951361

申请日：2020-11-18

Applicant: United Microelectronics Corp.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/3115 ,  H01L21/8238 ,  H01L27/092

Abstract: Provided is a manufacturing method of s semiconductor structure. The method includes: providing a substrate, wherein the substrate has a plurality of fin portions and at least one recessed portion, the at least one recessed portion is located between two adjacent fin portions of the plurality of fin portions and a bottom surface of the at least one recessed portion is lower than a surface of the substrate between the two of the plurality of fin portions; forming a doping layer on a sidewall of the plurality of fin portions, the surface of the substrate, and a sidewall and a bottom portion of the at least one recessed portion; and forming a dielectric layer on the doping layer. A top surface of the doping layer and a top surface of the dielectric layer are lower than a top surface of each of the plurality of fin portions.

公开(公告)号：US11244829B2

公开(公告)日：2022-02-08

申请号：US16136265

申请日：2018-09-20

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Yu-Cheng Tung ,  Fu-Che Lee

IPC: H01L21/308 ,  H01L21/033 ,  H01L27/108 ,  H01L21/3213

Abstract: A semiconductor device and a method of forming the same, the semiconductor includes a substrate and a material disposed on the substrate. The material layer includes plural first patterns arranged parallel and separately in an array within a first region of the substrate, and plural second patterns parallel and separately disposed at two opposite sides of the first patterns, and plural third patterns parallel and separately disposed at another two opposite sides of the first patterns, wherein each of the third patterns has a relative greater dimension than that of each of the first patterns.

公开(公告)号：US20220005802A1

公开(公告)日：2022-01-06

申请号：US17481300

申请日：2021-09-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Tung

IPC: H01L27/02 ,  H01L27/11 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092

Abstract: A layout of a semiconductor device and a method of forming a semiconductor device, the semiconductor device include a first fin and a second fin disposed on a substrate, a gate and a spacer. The first fin and the second fin both include two opposite edges, and the gate completely covers the two opposite edges of the first fin and only covers one sidewall of the two opposite edges of the second fin. The spacer is disposed at two sides of the gate, and the spacer covers another sidewall of the two opposite edges of the second fin.

公开(公告)号：US11011376B2

公开(公告)日：2021-05-18

申请号：US16242994

申请日：2019-01-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsiao-Pang Chou ,  Hon-Huei Liu ,  Ming-Chang Lu ,  Chin-Fu Lin ,  Yu-Cheng Tung

IPC: H01L21/76 ,  H01L21/02 ,  H01L29/20 ,  H01L29/06 ,  H01L21/308 ,  H01L21/306 ,  H01L23/00

Abstract: The present invention discloses a semiconductor structure with an epitaxial layer and method of manufacturing the same. The semiconductor structure with the epitaxial layer includes a substrate, a blocking layer on the substrate, multiple recesses formed in the substrate, wherein the recess extends along crystal faces of the substrate, and an epitaxial layer on the blocking layer, wherein the epitaxial layer is provided with a buried portion in each recess and an above-surface portion formed on the blocking layer.

公开(公告)号：US10983428B2

公开(公告)日：2021-04-20

申请号：US15978215

申请日：2018-05-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Chen Sun ,  Yu-Cheng Tung ,  Sheng-Yuan Hsueh

IPC: G06F30/39 ,  G03F1/36

Abstract: A mask includes a substrate, a main pattern, a first assist pattern, and a second assist pattern. The main pattern is disposed on the substrate. The main pattern includes a first pattern and second patterns. Two of the second patterns are disposed at two opposite sides of the first pattern in a first direction. The first assist pattern is disposed on the substrate and disposed in the main pattern. The second assist pattern is disposed on the substrate and disposed outside the main pattern. The first assist pattern disposed in the main pattern may be used to improve the pattern transferring performance in a photolithography process using the mask.