公开(公告)号：US07899264B2

公开(公告)日：2011-03-01

申请号：US11198650

申请日：2005-08-05

Applicant: Brian Douglas Stewart

Inventor： Brian Douglas Stewart

IPC: G06K9/40 ,  G02B7/04 ,  G02B27/40 ,  G02B27/64 ,  G03B13/00 ,  G03B27/52 ,  G03B13/32 ,  H04N5/232

CPC classification number: H04N5/23212 ,  G02B7/365 ,  G06T7/13

Abstract: The method of determining a focus measure from an image includes detecting one or more edges in the image by processing the image with one or more first order edge detection kernels adapted to reject edge phasing effects. A first measure of the strength of each of the edges, and the contrast of each of the edges may be determined. The method may include normalizing the first measure of the strength of each of the edges by the contrast of each of the edges to obtain a second measure of the strength of each of the edges, and resealing the second measure of the strength of each of the edges. The method may also include selecting one or more of the edges from the image in accordance with the second measure of their strengths, and calculating the focus measure from the second measure of the strengths of the selected edges.

Abstract translation: 从图像确定焦点测量的方法包括通过利用适于拒绝边缘相位效应的一个或多个第一阶边缘检测内核来处理图像来检测图像中的一个或多个边缘。 可以确定每个边缘的强度的第一测量以及每个边缘的对比度。 该方法可以包括通过每个边缘的对比来归一化每个边缘的强度的第一测量，以获得每个边缘的强度的第二测量，并且重新密封第二测量的每个边缘的强度 边缘。 该方法还可以包括根据其强度的第二测量从图像中选择一个或多个边缘，以及根据所选边缘的强度的第二测量来计算聚焦度量。

公开(公告)号：US20110025435A1

公开(公告)日：2011-02-03

申请号：US12650190

申请日：2009-12-30

Applicant: Oleksandr Gorbachov

Inventor： Oleksandr Gorbachov

IPC: H01P1/00 ,  G06F17/50

CPC classification number: G06F17/5036 ,  G06F2217/40 ,  H05K1/0243

Abstract: Pins on an RFIC package carry RF signals between the package and a PCB. A first capacitor is coupled between a selected pin of the RFIC package near the pins carrying the RF signals and a radio-frequency ground on the PCB. A coupling between the RFIC package and the PCB is modeled, and includes modeling of the pins of interest and at least one parasitic element of the coupling. A capacitance of the first capacitor is selected based on the modeling to obtain desired performance at selected operational frequencies. A second capacitor may be coupled between the selected pin a radio frequency ground of the RFIC package. An inductor may be coupled in parallel across the first capacitor.

Abstract translation: RFIC封装上的引脚在封装和PCB之间承载RF信号。 第一电容器耦合在RFIC封装的选定引脚附近，并承载RF信号的引脚和PCB上的射频接地。 RFIC封装和PCB之间的耦合被建模，并且包括关注引脚的建模和耦合的至少一个寄生元件。 基于建模来选择第一电容器的电容，以在选定的工作频率获得期望的性能。 所选引脚之间可以将第二电容器耦合到RFIC封装的射频接地。 电感器可以并联在第一电容器上。

公开(公告)号：US20100329321A1

公开(公告)日：2010-12-30

申请号：US12825278

申请日：2010-06-28

Applicant: Giuseppe Avellone ,  Oleksandr Gorbachov ,  Antonino Calcagno ,  Salvatore Scaccianoce

Inventor： Giuseppe Avellone ,  Oleksandr Gorbachov ,  Antonino Calcagno ,  Salvatore Scaccianoce

IPC: H04B17/00

CPC classification number: H04B1/0007 ,  H04B1/1027

Abstract: An electronic device includes an analog-to-digital converter adapted to receive a radio-frequency signal and adapted to provide therefrom a digital signal, wherein the radio-frequency signal may include an interference signal. The electronic device has a controller adapted to perform a digital measure on the digital signal and adapted to generate therefrom a selection signal having a first value indicating a non-interference condition in the radio-frequency signal and having a second value indicating an interference-condition in the radio-frequency signal. A selector is adapted to transmit the digital signal in case the selection signal has the first value and to transmit a signal replacing the digital signal in case the selection signal has the second value.

Abstract translation: 电子设备包括适于接收射频信号并适于从其提供数字信号的模拟 - 数字转换器，其中所述射频信号可以包括干扰信号。 电子设备具有控制器，适于对数字信号执行数字测量，并且适于从其产生具有指示射频信号中的非干扰状态的第一值的选择信号，并具有指示干扰条件的第二值 在射频信号中。 选择器适于在选择信号具有第一值的情况下发送数字信号，并且在选择信号具有第二值的情况下发送替换数字信号的信号。

公开(公告)号：US07447385B2

公开(公告)日：2008-11-04

申请号：US11015242

申请日：2004-12-17

Applicant: Jeffrey Raynor

Inventor： Jeffrey Raynor

IPC: G06K7/00 ,  G01N21/59 ,  H04N1/04

CPC classification number: G01N21/6454 ,  G01N21/253 ,  G01N21/274 ,  G01N21/6428 ,  G01N21/75

Abstract: A bio-optical sensor has a surface provided with an array of sensing pixels and calibration pixels. The sensing and calibration pixels are arranged in an interleaved fashion. The sensing and calibration pixels may be interleaved 1:1, or they may be arranged in interleaved blocks. The image plane receives an analyte and a reagent that reacts with the analyte to produce light. The sensing pixels generate signals as a function of the light produced.

Abstract translation: 生物光学传感器具有设置有感测像素和校准像素阵列的表面。 感测和校准像素以交错方式排列。 感测和校准像素可以交织1：1，或者它们可以被布置在交错块中。 图像平面接收分析物和与分析物反应产生光的试剂。 感测像素产生作为产生的光的函数的信号。

公开(公告)号：US07446626B2

公开(公告)日：2008-11-04

申请号：US11530220

申请日：2006-09-08

Applicant: Oleksandr Gorbachov

Inventor： Oleksandr Gorbachov

IPC: H03K7/04

CPC classification number: G01R27/06 ,  H01P5/185 ,  H03H7/46 ,  H03H7/48

Abstract: Very small size true directional couplers have a coupling coefficient that is independent on load VSWR. The coupler uses coupled inductors with a compensation circuit including a resistor and a capacitor, or just a capacitor. Wideband operation is suitable for many portable applications such as power detection and control for GSM, DCS-PCS, CDMA/WCDMA, Bluetooth, and WLAN systems.

Abstract translation: 非常小尺寸的真正定向耦合器具有独立于负载VSWR的耦合系数。 耦合器使用具有包括电阻器和电容器的补偿电路的耦合电感器，或仅仅是电容器。 宽带操作适用于许多便携式应用，如GSM，DCS-PCS，CDMA / WCDMA，蓝牙和WLAN系统的功率检测和控制。

公开(公告)号：US07346072B2

公开(公告)日：2008-03-18

申请号：US10780355

申请日：2004-02-17

Applicant: Andrew M. Jones ,  John A. Carey

Inventor： Andrew M. Jones ,  John A. Carey

IPC: H04L12/43

CPC classification number: H04L45/00

Abstract: A pipelined arbitration mechanism allows a routing control decision to be effected for a later packet while a current packet is being transferred. The later packet can be issued a fixed number of cycles after the current request. The mechanism has particular advantages when used with a plurality of functional modules connected to a packet router, whereby a single functional module can generate a current request relating to a current packet and a deferred arbitration request relating to a later packet to be issued a fixed number of cycles after the current request.

Abstract translation: 流水线仲裁机制允许在当前分组正在传输时对稍后的分组进行路由控制决定。 稍后的数据包可以在当前请求之后发出固定数量的周期。 当与连接到分组路由器的多个功能模块一起使用时，该机制具有特别的优点，由此单个功能模块可以生成与当前分组有关的当前请求以及与要发布固定数量的稍后分组有关的延迟仲裁请求 的当前请求后的周期。

公开(公告)号：US07288801B2

公开(公告)日：2007-10-30

申请号：US10786878

申请日：2004-02-25

Applicant: Jeffrey Raynor

Inventor： Jeffrey Raynor

IPC: H01L31/0328

CPC classification number: H01L27/1443 ,  H01L27/14609

Abstract: A CMOS image sensing structure includes a photodiode, in which an epitaxial layer is on a P-type substrate. The photodiode includes an N-well collection node in the epitaxial layer. An isolation trench is provided around the collection node to provide better control of the width of the collection node. The collection node can be surrounded by P-wells or by epitaxial material. It can also be surrounded by epitaxial material with the isolation trench being outwardly extended to ensure compliance with existing design rules.

Abstract translation: CMOS图像感测结构包括其中外延层在P型衬底上的光电二极管。 光电二极管包括外延层中的N阱收集节点。 在收集节点周围设置隔离沟槽，以便更好地控制收集节点的宽度。 采集节点可以被P阱或外延材料包围。 它也可以被外延材料包围，隔离槽向外延伸以确保符合现有的设计规则。

公开(公告)号：US07280140B2

公开(公告)日：2007-10-09

申请号：US10405101

申请日：2003-04-01

Applicant: Robert Henderson

Inventor： Robert Henderson

IPC: H04N5/217 ,  H04N9/64

CPC classification number: H04N5/3575 ,  H04N5/363 ,  H04N5/374

Abstract: A solid state image sensor has an array of pixels in which each column has a reset voltage line and a read line. The sensor is reset and read a row at a time, with reset-related values held in a frame buffer for subsequent subtraction from read values. Reset-related values are derived in each column by sampling the voltage during reset on one capacitor and the voltage on release of reset on a second capacitor, and differencing these values to provide an output for the frame buffer. This provides a reduction in the size of frame buffer which would otherwise be required.

Abstract translation: 固态图像传感器具有其中每列具有复位电压线和读取线的像素阵列。 传感器一次复位并读取一行，复位相关值保持在帧缓冲器中，以便随后从读取值中减去。 通过在一个电容器的复位期间对电压进行采样，在第二个电容器上进行复位时的电压，并对这些值进行差分以提供帧缓冲器的输出，从而在每列中得到复位相关值。 这样可以减少否则将需要的帧缓冲区的大小。

公开(公告)号：US07260745B1

公开(公告)日：2007-08-21

申请号：US09410642

申请日：1999-10-01

Applicant: David A. Edwards ,  Andrew M. Jones ,  Anthony W. Rich

Inventor： David A. Edwards ,  Andrew M. Jones ,  Anthony W. Rich

IPC: G06F11/00

CPC classification number: G06F11/3636 ,  G06F11/364 ,  G06F11/3648

Abstract: In a system comprising an interconnect and a plurality of modules connected to said interconnect for putting information onto the interconnect, a circuit comprising circuitry for receiving at least part of said of said information; circuitry for determining if said at least part of said information satisfies one or more conditions; and circuitry for performing one or more actions in response to the determination that at least part of the information satisfies one or more conditions.

Abstract translation: 在包括互连和连接到所述互连以将信息放置到互连上的多个模块的系统中，包括用于接收所述信息的至少一部分的电路的电路; 用于确定所述信息的至少一部分是否满足一个或多个条件的电路; 以及用于响应于至少部分信息满足一个或多个条件的确定而执行一个或多个动作的电路。

公开(公告)号：US07228389B2

公开(公告)日：2007-06-05

申请号：US11313261

申请日：2005-12-20

Applicant: Andrew M. Jones ,  John Carrey

Inventor： Andrew M. Jones ,  John Carrey

IPC: G06F12/00

CPC classification number: G06F12/0833

Abstract: A data processing system having shared memory accessible through a transaction-based bus mechanism. A plurality of system components, including a central processor, are coupled to the bus mechanism. The bus mechanism includes a cache coherency transaction within its transaction set. The cache coherency transaction comprises a request issued by one of the system components that is recognized by a cache unit of the central processor as an explicit command to perform a cache coherency operation. The transaction further comprises a response issued by the central processor indicating status of the cache coherency operation.

Abstract translation: 具有通过基于事务的总线机制可访问的共享存储器的数据处理系统。 包括中央处理器的多个系统组件耦合到总线机构。 总线机制包括其事务集中的高速缓存一致性事务。 高速缓存一致性事务包括由中央处理器的高速缓存单元识别的系统组件之一发出的请求作为执行高速缓存一致性操作的显式命令。 交易还包括由中央处理器发出的指示高速缓存一致性操作的状态的响应。