公开(公告)号：US20210296157A1

公开(公告)日：2021-09-23

申请号：US17334928

申请日：2021-05-31

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist

IPC: H01L21/74 ,  H01L21/768 ,  H01L21/822 ,  H01L27/11582 ,  H01L27/11556

Abstract: A method to form a 3D semiconductor device, the method including: providing a first level including first circuits, the first circuits including first transistors and first interconnection; preparing a second level including a silicon layer; forming second circuits over the second level, the second circuits including second transistors and second interconnection; transferring with bonding the second level on top of the first level; and then thinning the second level to a thickness of less than thirty microns, where the bonding includes oxide to oxide bonds, where the bonding includes metal to metal bonds, and where at least one of the metal to metal bond structures has a pitch of less than 1 micron from another of the metal to metal bond structures.

公开(公告)号：US11121021B2

公开(公告)日：2021-09-14

申请号：US16101489

申请日：2018-08-12

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar ,  Zeev Wurman

IPC: H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11578 ,  H01L21/683 ,  G11C8/16 ,  H01L29/792 ,  H01L29/788 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L27/12 ,  H01L27/118 ,  H01L27/11573 ,  H01L27/11526 ,  H01L27/112 ,  H01L27/11 ,  H01L27/108 ,  H01L27/105 ,  H01L27/10 ,  H01L27/092 ,  H01L27/06 ,  H01L27/02 ,  H01L23/525 ,  H01L23/48 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/822 ,  H01L21/768 ,  H01L21/762 ,  H01L21/74 ,  H01L49/02 ,  H01L27/088 ,  H01L29/732 ,  H01L29/737 ,  H01L21/8234 ,  H01L29/786 ,  H01L29/06 ,  H01L29/775 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L23/367 ,  H01L23/544 ,  H01L27/24 ,  H01L45/00

Abstract: A 3D semiconductor device, including: a first level including a single crystal layer, a plurality of first transistors, and a first metal layer, forming memory control circuits; a second level overlaying the single crystal layer, and including a plurality of second transistors and a plurality of first memory cells; a third level overlaying the second level, and including a plurality of third transistors and a plurality of second memory cells; where the second transistors are aligned to the first transistors with less than 40 nm alignment error, where the memory cells include a NAND non-volatile memory type, where some of the memory control circuits can control at least one of the memory cells, and where some of the memory control circuits are designed to perform a verify read after a write pulse so to detect if the at least one of the memory cells has been successfully written.

公开(公告)号：US11114464B2

公开(公告)日：2021-09-07

申请号：US17063397

申请日：2020-10-05

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han

IPC: H01L27/11582 ,  H01L29/47 ,  H01L29/78 ,  H01L29/167 ,  H01L23/528 ,  H01L27/02 ,  H01L27/11578 ,  H01L29/792 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11514 ,  H01L27/11551

Abstract: A 3D device, the device including: a first level including logic circuits; a second level including a plurality of dynamic memory cells; and a third level including a plurality of non-volatile memory cells, where the first level is bonded to the second level, and where the device includes refresh circuits to refresh the dynamic memory cells.

公开(公告)号：US20210272835A1

公开(公告)日：2021-09-02

申请号：US17306627

申请日：2021-05-03

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC: H01L21/683 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/48 ,  H01L23/525 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  H01L27/112 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  G11C8/16

Abstract: A semiconductor device, the device including: a first single crystal substrate and plurality of logic circuits, where the first single crystal substrate has a device area, where the device area is significantly larger than a reticle size, where the plurality of logic circuits include an array of processors, where the plurality of logic circuits include a first logic circuit, a second logic circuit, and third logic circuit, where the plurality of logic circuits include switching circuits to support replacing the first logic circuit and the second logic circuit by the third logic circuit; and a second single crystal substrate, where the second single crystal substrate is disposed atop the first single crystal substrate.

公开(公告)号：US11101266B2

公开(公告)日：2021-08-24

申请号：US17026146

申请日：2020-09-18

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L27/06 ,  H01L29/66 ,  H01L29/45 ,  H01L29/786 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/812 ,  H01L29/423 ,  H01L29/732 ,  H01L29/808 ,  H01L21/768 ,  H01L21/822 ,  H01L23/367 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  G03F9/00 ,  H01L21/762 ,  H01L21/84 ,  H01L23/48 ,  H01L23/544 ,  H01L27/02 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  H01L27/112 ,  H01L27/11551 ,  H01L27/11578 ,  H01L27/118 ,  H01L27/12 ,  H01L23/00 ,  H01L21/268 ,  H01L27/088

Abstract: A 3D device including: a first level including first single crystal transistors overlaid by a second level including second single crystal transistors; a third level including third single crystal transistors, the second level is overlaid by the third level; a fourth level including fourth single crystal transistors, the third level is overlaid by the fourth level; first bond regions including first oxide to oxide bonds, where the first bond regions are between the first level and the second level; second bond regions including second oxide to oxide bonds, where the second bond regions are between the second level and the third level; and third bond regions including third oxide to oxide bonds, where the third bond regions are between the third level and the fourth level, where the second level, third level, and fourth level each include one array of memory cells, and where the one array of memory cells is a DRAM type memory.

公开(公告)号：US20210256192A1

公开(公告)日：2021-08-19

申请号：US17306948

申请日：2021-05-04

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Zeev Wurman

IPC: G06F30/392 ,  G06F30/394

Abstract: A method of designing a 3D Integrated Circuit, the method comprising: performing partitioning to at least a logic strata comprising logic and a memory strata comprising memory; then performing a first placement of said logic strata using a 2D placer executed by a computer, wherein said 2D placer is a Computer Aided Design (CAD) tool for two-dimensional devices, wherein said 3D Integrated Circuit comprises through silicon vias for connection between said logic strata and said memory strata; and performing a second placement of said memory strata based on said first placement, wherein said memory comprises a first memory array, wherein said logic comprises a first logic circuit controlling said first memory array, wherein said first placement comprises placement of said first logic circuit, and wherein said second placement comprises placement of said first memory array based on said placement of said first logic circuit.

公开(公告)号：US20210217643A1

公开(公告)日：2021-07-15

申请号：US17214806

申请日：2021-03-27

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC: H01L21/683 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/48 ,  H01L23/525 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  H01L27/112 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  G11C8/16

Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where the first transistors each include a single crystal channel; first metal layers interconnecting at least the first transistors; and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where the second level is bonded to the first level, where the bonded includes oxide to oxide bonds, where the bonded includes metal to metal bonds, and where through the first metal layers power is provided to at least one of the second transistors.

公开(公告)号：US20210193722A1

公开(公告)日：2021-06-24

申请号：US17143956

申请日：2021-01-07

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L27/146 ,  H01L27/148 ,  H01L23/544

Abstract: An integrated device, the device including: a first level including a first mono-crystal layer, the first mono-crystal layer including a plurality of single crystal transistors and alignment marks; an overlaying oxide on top of the first level; a second level including a second mono-crystal layer, the second level overlaying the oxide, where the second mono-crystal layer includes a plurality of first image sensors; and a third level overlaying the second level, where the third level includes a plurality of second image sensors, where the second level is aligned to the alignment marks, where the second level is bonded to the first level, and where the bonded includes an oxide to oxide bond.

公开(公告)号：US20210193655A1

公开(公告)日：2021-06-24

申请号：US17169511

申请日：2021-02-07

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist

IPC: H01L27/088 ,  H01L27/06 ,  H01L21/822 ,  H01L27/118

Abstract: A 3D semiconductor device including: a first level, which includes a first layer, the first layer including first transistors, and where the first level includes a second layer, the second layer including first interconnections; a second level overlaying the first level, where the second level includes a third layer including second transistors, and where the second level includes a fourth layer, the fourth layer including second interconnections; a plurality of connection paths, where the paths provide connections from a plurality of the first transistors to a plurality of second transistors, where the second level is bonded to the first level, where the bonded includes oxide to oxide bond regions and metal to metal bond regions, where the second level includes at least one memory array, and where the third layer includes crystalline silicon; and a heat removal path from the first layer or the third layer to an external surface of the device.

公开(公告)号：US11043523B1

公开(公告)日：2021-06-22

申请号：US17143956

申请日：2021-01-07

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L27/146 ,  H01L27/148 ,  H01L23/544 ,  H01L21/762

Abstract: An integrated device, the device including: a first level including a first mono-crystal layer, the first mono-crystal layer including a plurality of single crystal transistors and alignment marks; an overlaying oxide on top of the first level; a second level including a second mono-crystal layer, the second level overlaying the oxide, where the second mono-crystal layer includes a plurality of first image sensors; and a third level overlaying the second level, where the third level includes a plurality of second image sensors, where the second level is aligned to the alignment marks, where the second level is bonded to the first level, and where the bonded includes an oxide to oxide bond.