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公开(公告)号：US11353905B2
公开(公告)日：2022-06-07
申请号：US16787679
申请日：2020-02-11
Inventor： Jean Camiolo , Alexandre Pons
IPC: G05F1/575 , G01R19/165 , G05F3/18 , G06F1/26 , H03F3/45 , H03K3/0233 , G05F1/56
Abstract: A first terminal receives a first DC voltage. A switch selectively couples the first terminal to a second terminal providing an output. A control circuit selectively actuates the switch in response to a comparison of the first DC voltage to a second DC voltage. A low-dropout (LDO) linear voltage regulator, connected between the first and third terminals, operates to provide the second DC voltage from the first DC voltage.
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公开(公告)号：US11283353B2
公开(公告)日：2022-03-22
申请号：US16385284
申请日：2019-04-16
Applicant: STMicroelectronics S.r.l. , STMicroelectronics (Alps) SAS
Inventor： Francois Druilhe , Patrik Arno , Alessandro Inglese , Michele Alessandro Carrano
Abstract: A power supply system includes a voltage application source, and a switched mode power supply having an output coupled to the voltage application source through a first path and through a second path different from the first path. A first node is coupled to the output of the switched mode power supply, the switched mode power supply being configured to couple the first node to the voltage application source through the first path in a first operating mode and through the second path in a different second operating mode. A digital regulator is coupled to the first node. A digital circuit is coupled to an output of the digital regulator. An analog regulator is coupled to the first node and an analog circuit coupled to an output of the analog regulator.
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公开(公告)号：US20220028844A1
公开(公告)日：2022-01-27
申请号：US17374868
申请日：2021-07-13
Inventor： Deborah COGONI , David AUCHERE , Laurent SCHWARTZ , Claire Laporte
Abstract: A device for regulating a voltage of an electric current supplying an integrated circuit resting on a substrate. The integrated circuit comprises a ground terminal and a power supply terminal able to receive the electric current. The regulation device comprises a first cover covering the integrated circuit, a second cover covering the integrated circuit. The first cover is electrically connected to the power supply terminal of the integrated circuit. The second cover is electrically connected to the ground terminal of the integrated circuit. The first cover and the second cover are connected together by a capacitive connection.
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公开(公告)号：US20220004217A1
公开(公告)日：2022-01-06
申请号：US17480803
申请日：2021-09-21
Applicant: STMICROELECTRONICS (ALPS) SAS
Inventor： Kuno Lenz
Abstract: In an embodiment, a device for generating a first current from a second current, comprises: an output transistor configured to generate the first current; a first circuit configured to generate a third current representative of the second current and to draw it from a first node; a second circuit configured to generate a fourth current representative of the first current and to supply it to the first node; and a third circuit receiving a fifth current representative of a difference between the third and fourth currents, the third circuit being configured to generate a sixth current representative of the fifth current and to draw it from a control terminal of the output transistor.
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公开(公告)号：US11115061B2
公开(公告)日：2021-09-07
申请号：US17010351
申请日：2020-09-02
Inventor： Fabrice Romain , Mathieu Lisart , Patrick Arnould
Abstract: A datum is written to a memory, by splitting a binary word, representative of the datum and an error correcting or detecting code, into a first part and a second part. The first part is written at a logical address in a first memory circuit. The second part is written at the logical address in a second memory circuit. The error correcting or detecting code is dependent on both the datum and the logical address.
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Patent Agency Ranking
216.发明申请公开(公告)号：US20210240862A1
公开(公告)日：2021-08-05
申请号：US17161194
申请日：2021-01-28
Inventor： Gilles PELISSIER , Nicolas ANQUET , Delphine LE-GOASCOZ
Abstract: An integrated circuit includes a secure hardware environment having a first input that receives a key number. A key generation device generates a secret key from the key number and a unique key. A signature generation device generates a signature associated with the key number. A second input of the secure hardware environment receives encrypted binary data. A decryption device operates to decrypt the received encrypted binary data using the secret key. A third input the secure hardware environment receives an authentication signature. An authentication device authorizes use of the secret key to decrypt only if the signature generated by the signature generation device is identical to the authentication signature.
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公开(公告)号：US20210234362A1
公开(公告)日：2021-07-29
申请号：US17157555
申请日：2021-01-25
Applicant: STMicroelectronics (Alps) SAS
Inventor： Michel Bouche
Abstract: An embodiment of the present disclosure relates to an electronic circuit including a first switch coupling a first node of the circuit to an input/output terminal of the circuit; a second switch coupling the first node to a second node of application of a fixed potential; and a high-pass filter having an input coupled to the terminal and an output coupled to a control terminal of the second switch.
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公开(公告)号：US11070754B1
公开(公告)日：2021-07-20
申请号：US16828423
申请日：2020-03-24
Inventor： Hongliang Zhang , Lookah Chua , Celine Mas , Wai Yin Hnin
Abstract: In an embodiment, an image sensor includes: first and second voltage rails; first and second regulators configured to generate first and second regulated voltage at the first and second voltage rails, respectively; and a plurality of pixels coupled to the first and second voltage rails. Each pixel includes: first and second transistor coupled first and second storage capacitor, respectively. A third transistor is coupled between a control terminal of the first transistor and the first or second voltage rails. The third transistor is configured to limit a slew rate of current flowing between the control terminal of the second transistor and the first or second voltage rails to a first slew rate when the image sensor operates in global shutter mode, and to a second slew rate when the image sensor operates in rolling mode, the first slew rate being smaller than the second slew rate.
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公开(公告)号：US20210157668A1
公开(公告)日：2021-05-27
申请号：US16953993
申请日：2020-11-20
Applicant: STMicroelectronics (Rousset) SAS , STMicroelectronics (Alps) SAS , STMicroelectronics (Grand Ouest) SAS
Inventor： Loic Pallardy , Nicolas Anquet , Dragos Davidescu
Abstract: In an embodiment a system on chip includes a plurality of microprocessors, a plurality of slave resources, an interconnection circuit coupled between the microprocessors and the slave resources, the interconnection circuit configured to route transactions between the microprocessors and the slave resources and a processing controller configured to allow a user of the system to implement within the system at least one configuration diagram of the system defined by a set of configuration pieces of information used to define an assignment of at least one microprocessor to at least some of the slave resources, select the at least one microprocessors, and authorise an external debugging tool to access, for debugging purposes, only the slave resources assigned to the at least one microprocessor.
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公开(公告)号：US20200336138A1
公开(公告)日：2020-10-22
申请号：US16849020
申请日：2020-04-15
Applicant: STMicroelectronics S.r.l. , STMicroelectronics (Alps) SAS
Abstract: An H-bridge circuit includes a supply voltage node, a first pair of transistors and a second pair of transistors. First transistors in each pair have the current paths therethrough included in current flow lines between the supply node and, respectively, a first output node and a second output node. Second transistors in each pair have the current paths therethrough coupled to a third output node and a fourth output node, respectively. The first and third output nodes are mutually isolated from each other and the second and fourth output nodes are mutually isolated from each other. The H-bridge circuit is operable in a selected one of a first, second and third mode.
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