公开(公告)号：US11562927B2

公开(公告)日：2023-01-24

申请号：US17228164

申请日：2021-04-12

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Didier Dutartre ,  Jean-Pierre Carrere ,  Jean-Luc Huguenin ,  Clement Pribat ,  Sarah Kuster

IPC: H01L21/768 ,  H01L21/82 ,  H01L21/84 ,  H01L21/762 ,  H01L21/74 ,  H01L21/02 ,  H01L29/06 ,  H01L27/12 ,  H01L21/8234

Abstract: A silicon on insulator substrate includes a semiconductor bulk handle wafer, an insulating layer on said semiconductor bulk handle wafer and a semiconductor film on said insulating layer. An opening extends completely through the semiconductor film and insulating layer to expose a surface of the semiconductor bulk handle wafer. Epitaxial material fills the opening and extends on said semiconductor film, with the epitaxial material and semiconductor film forming a thick semiconductor film. A trench isolation surrounds a region of the thick semiconductor film to define an electrical contact made to the semiconductor bulk handle wafer through the opening.

公开(公告)号：US20230012522A1

公开(公告)日：2023-01-19

申请号：US17935754

申请日：2022-09-27

Applicant: STMICROELECTRONICS (CROLLES 2) SAS ,  STMICROELECTRONICS (ROUSSET) SAS

Inventor： Franck JULIEN ,  Stephan NIEL ,  Leo GAVE

IPC: H01L29/40 ,  H01L29/51 ,  H01L29/66

Abstract: A method for manufacturing an electronic device includes locally implanting ionic species into a first region of a silicon nitride layer and into a first region of an electrically insulating layer located under the first region of the silicon nitride layer. A second region of the silicon nitride layer and a region of the electrically insulating layer located under the second region of the silicon nitride layer are protected from the implantation. The electrically insulating layer is disposed between a semi-conducting substrate and the silicon nitride layer. At least one trench is formed extending into the semi-conducting substrate through the silicon nitride layer and the electrically insulating layer. The trench separates the first region from the second region of the electrically insulating layer. The electrically insulating layer is selectively etched, and the etch rate of the electrically insulating layer in the first region is greater than the etch rate in the second region.

公开(公告)号：US11552116B2

公开(公告)日：2023-01-10

申请号：US17011900

申请日：2020-09-03

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Thomas Dalleau

IPC: H04N5/3745 ,  H01L27/146

Abstract: A pixel includes a photodiode and first and second transistors, the first and second transistors being coupled in series. One of the first and second transistors is a P channel transistor and the other is an N channel transistor. An electronic device may include one or more of the pixels.

公开(公告)号：US20220406837A1

公开(公告)日：2022-12-22

申请号：US17840027

申请日：2022-06-14

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois ROY

IPC: H01L27/146

Abstract: A photosensitive sensor includes a pixel formed by a photosensitive region in a first semiconductor material, a read region in a second semiconductor material, and a transfer gate facing the parts of the first semiconductor material and the second semiconductor material located between the photosensitive region and the read region. The first semiconductor material and the second semiconductor material have different band gaps and are in contact with one another to form a heterojunction facing the transfer gate.

公开(公告)号：US11515415B2

公开(公告)日：2022-11-29

申请号：US17095003

申请日：2020-11-11

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Jean Jimenez Martinez

IPC: H01L29/78 ,  H01L27/06 ,  H01L29/66 ,  H01L29/73 ,  H01L29/06

Abstract: An integrated circuit includes an N-type laterally diffused metal-oxide semiconductor (NLDMOS) transistor including an active semiconductor substrate region having P-type conductivity. The integrated circuit further includes a buried semiconductor region having N+-type conductivity underneath the active substrate region. The buried semiconductor region is more heavily doped than the active semiconductor substrate region.

公开(公告)号：US20220359435A1

公开(公告)日：2022-11-10

申请号：US17733589

申请日：2022-04-29

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics International N.V.

Inventor： Stephane MONFRAY ,  Siddhartha DHAR ,  Alain FLEURY

IPC: H01L23/66 ,  H01L23/373 ,  H01L23/42 ,  H01L21/48

Abstract: The present disclosure relates to an electronic circuit comprising a semiconductor substrate, radiofrequency switches corresponding to MOS transistors comprising doped semiconductor regions in the substrate, at least two metallization levels covering the substrate, each metallization level comprising a stack of insulating layers, conductive pillars topped by metallic tracks, at least two connection elements each connecting one of the doped semiconductor regions and formed by conductive pillars and conductive tracks of each metallization level. The electronic circuit further comprises, between the two connection elements, a trench crossing completely the stack of insulating layers of one metallization level and further crossing partially the stack of insulating layers of the metallization level the closest to the substrate, and a heat dissipation device adapted for dissipating heat out of the trench.

公开(公告)号：US20220344385A1

公开(公告)日：2022-10-27

申请号：US17724739

申请日：2022-04-20

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois GUYADER

IPC: H01L27/146

Abstract: A semiconductor substrate includes a matrix of photosites. Each photosite is delimited by an isolation trench including polycrystalline silicon. A peripheral zone extends directly around the matrix of photosites. The peripheral zone includes dummy photosites delimited by isolation trenches including polycrystalline silicon. A density of polycrystalline silicon in the peripheral zone is between a density of polycrystalline silicon at an edge of the matrix of photosites and a density of polycrystalline silicon around the peripheral zone.

公开(公告)号：US11451730B2

公开(公告)日：2022-09-20

申请号：US16890877

申请日：2020-06-02

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Pierre Malinge ,  Frederic Lalanne ,  Laurent Simony

IPC: H04N5/3745 ,  H04N5/355

Abstract: An image sensor includes pixels each including: a first transistor and a first switch that are connected in series between a first node configured to receive a first potential and an internal node of the pixel, a gate of the first transistor being coupled with a floating diffusion node of the pixel; a capacitive element, a first terminal of which is connected to the floating diffusion node of the pixel; and several assemblies each including a capacitance connected in series with a second switch coupling the capacitance to the internal node. The sensor also includes a control circuit configured to control, each time a voltage is stored in one of the assemblies of a pixel, an increase of a determined value of a difference in potential between the floating diffusion node and the internal node of the pixel.

公开(公告)号：US11444110B2

公开(公告)日：2022-09-13

申请号：US17225329

申请日：2021-04-08

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Boris Rodrigues Goncalves ,  Frederic Lalanne

IPC: H01L27/146 ,  H04N5/369 ,  H04N5/378

Abstract: A pixel includes a photoconversion zone, an insulated vertical electrode and at least one charge storage zone. The photoconversion zone belongs to a first part of a semiconductor substrate and each charge storage zone belongs to a second part of the substrate physically separated from the first part of the substrate by the insulated vertical electrode.

公开(公告)号：US11387379B2

公开(公告)日：2022-07-12

申请号：US16789052

申请日：2020-02-12

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy

IPC: H01L31/113 ,  H01L31/0224 ,  H01L27/146

Abstract: A semiconductor layer is doped with a first doping type and has an upper surface. A first electrode insulated from the semiconductor layer extending through the semiconductor layer from the upper surface. A second electrode insulated from the semiconductor layer extends through the semiconductor layer from the upper surface. The first and second electrodes are biased by a voltage to produce an electrostatic field within the semiconductor layer causing the formation of a depletion region. The depletion region responds to absorption of a photon with an avalanche multiplication that produces charges that are collected at first and second oppositely doped regions within the semiconductor substrate.