公开(公告)号：US11515415B2

公开(公告)日：2022-11-29

申请号：US17095003

申请日：2020-11-11

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Jean Jimenez Martinez

IPC: H01L29/78 ,  H01L27/06 ,  H01L29/66 ,  H01L29/73 ,  H01L29/06

Abstract: An integrated circuit includes an N-type laterally diffused metal-oxide semiconductor (NLDMOS) transistor including an active semiconductor substrate region having P-type conductivity. The integrated circuit further includes a buried semiconductor region having N+-type conductivity underneath the active substrate region. The buried semiconductor region is more heavily doped than the active semiconductor substrate region.

公开(公告)号：US11823947B2

公开(公告)日：2023-11-21

申请号：US17978533

申请日：2022-11-01

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Jean Jimenez Martinez

IPC: H01L21/74 ,  H01L27/06 ,  H01L29/66 ,  H01L29/73 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8249 ,  H01L21/266 ,  H01L21/02

CPC classification number: H01L21/74 ,  H01L21/02 ,  H01L21/266 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/0615 ,  H01L29/66234 ,  H01L29/66681 ,  H01L29/7302 ,  H01L29/7816 ,  H01L29/7817

Abstract: An integrated circuit includes an N-type laterally diffused metal-oxide semiconductor (NLDMOS) transistor including an active semiconductor substrate region having P-type conductivity. The integrated circuit further includes a buried semiconductor region having N+-type conductivity underneath the active substrate region. The buried semiconductor region is more heavily doped than the active semiconductor substrate region.

公开(公告)号：US11342449B2

公开(公告)日：2022-05-24

申请号：US17095230

申请日：2020-11-11

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Jean Jimenez Martinez

IPC: H01L29/808 ,  H01L29/66 ,  H01L21/8248 ,  H01L27/06 ,  H01L29/06 ,  H01L29/423 ,  H01L27/112

Abstract: An integrated circuit includes a junction field-effect transistor formed in a semiconductor substrate. The junction field-effect transistor includes a drain region, a source region, a channel region, and a gate region. A first isolating region separates the drain region from both the gate region and the channel region. A first connection region connects the drain region to the channel region by passing underneath the first isolating region in the semiconductor substrate. A second isolating region separates the source region from both the gate region and the channel region. A second connection region connects the source region to the channel region by passing underneath the second isolating region in the semiconductor substrate.

公开(公告)号：US11538719B2

公开(公告)日：2022-12-27

申请号：US17160598

申请日：2021-01-28

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Jean Jimenez Martinez

IPC: H01L21/82 ,  H01L21/8228 ,  H01L27/082

Abstract: A microelectronic device includes a PNP transistor and NPN transistor arranged vertically in a P-type doped semiconductor substrate. The PNP and NPN transistors are manufactured by: forming an N+ doped isolating well for the PNP transistor in the semiconductor substrate; forming a P+ doped region in the N+ doped isolating well; epitaxially growing a first semiconductor layer on the semiconductor substrate; forming an N+ doped well for the NPN transistor, where at least part of the N+ doped well extends into the first semiconductor layer; then epitaxially growing a second semiconductor layer on the first semiconductor layer; forming a P doped region forming the collector of the PNP transistor in the second semiconductor layer and in electrical contact with the P+ doped region; and forming an N doped region forming the collector of the NPN transistor in the second semiconductor layer and in electrical contact with the N+ doped well.

公开(公告)号：US11955481B2

公开(公告)日：2024-04-09

申请号：US17992602

申请日：2022-11-22

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Jean Jimenez Martinez

IPC: H01L27/08 ,  H01L21/8228 ,  H01L27/082

CPC classification number: H01L27/0826 ,  H01L21/82285

Abstract: A microelectronic device includes a PNP transistor and NPN transistor arranged vertically in a P-type doped semiconductor substrate. The PNP and NPN transistors are manufactured by: forming an N+ doped isolating well for the PNP transistor in the semiconductor substrate; forming a P+ doped region in the N+ doped isolating well; epitaxially growing a first semiconductor layer on the semiconductor substrate; forming an N+ doped well for the NPN transistor, where at least part of the N+ doped well extends into the first semiconductor layer; then epitaxially growing a second semiconductor layer on the first semiconductor layer; forming a P doped region forming the collector of the PNP transistor in the second semiconductor layer and in electrical contact with the P+ doped region; and forming an N doped region forming the collector of the NPN transistor in the second semiconductor layer and in electrical contact with the N+ doped well.

公开(公告)号：US11830776B2

公开(公告)日：2023-11-28

申请号：US17730691

申请日：2022-04-27

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Jean Jimenez Martinez

IPC: H01L21/82 ,  H01L21/8248 ,  H01L27/06 ,  H01L29/06 ,  H01L29/66 ,  H01L29/808 ,  H01L29/423 ,  H10B20/00 ,  H01L21/62 ,  H01L21/04

CPC classification number: H01L21/8248 ,  H01L21/046 ,  H01L21/0415 ,  H01L21/62 ,  H01L27/0623 ,  H01L29/0653 ,  H01L29/42376 ,  H01L29/66893 ,  H01L29/808 ,  H10B20/40

Abstract: An integrated circuit includes a junction field-effect transistor formed in a semiconductor substrate. The junction field-effect transistor includes a drain region, a source region, a channel region, and a gate region. A first isolating region separates the drain region from both the gate region and the channel region. A first connection region connects the drain region to the channel region by passing underneath the first isolating region in the semiconductor substrate. A second isolating region separates the source region from both the gate region and the channel region. A second connection region connects the source region to the channel region by passing underneath the second isolating region in the semiconductor substrate.