公开(公告)号：US20150008520A1

公开(公告)日：2015-01-08

申请号：US13933642

申请日：2013-07-02

Applicant: International Business Machines Corporation ,  Commissariat A I'Energie atomique et aux Energies alternatives ,  STMicroelectronics, Inc.

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Qing Liu ,  Laurent Grenouillet ,  Yannick Le Tiec ,  Maud Vinet

IPC: H01L27/12 ,  H01L21/02 ,  H01L21/762

CPC classification number: H01L27/1207 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/84 ,  H01L29/0649 ,  H01L29/1608 ,  H01L29/161

Abstract: Trenches are formed through a top semiconductor layer and a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A selective epitaxy is performed to form bulk semiconductor portions filling the trenches and in epitaxial alignment with the semiconductor material of a handle substrate. At least one dielectric layer is deposited over the top semiconductor layer and the bulk semiconductor portions, and is patterned to form openings over selected areas of the top semiconductor layer and the bulk semiconductor portions. A semiconductor alloy material is deposited within the openings directly on physically exposed surfaces of the top semiconductor layer and the bulk semiconductor portions. The semiconductor alloy material intermixes with the underlying semiconductor materials in a subsequent anneal. Within each of the SOI region and the bulk region, two types of semiconductor material portions are formed depending on whether a semiconductor material intermixes with the semiconductor alloy material.

公开(公告)号：US20140353753A1

公开(公告)日：2014-12-04

申请号：US13906677

申请日：2013-05-31

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Shom Ponoth ,  Prasanna Khare ,  Qing Liu ,  Balasubramanian Pranatharthiharan

IPC: H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/7848 ,  H01L29/785

Abstract: Improved fin field effect transistor (FinFET) devices and methods for fabrication thereof. In one aspect, a method for fabricating a FinFET device comprises: a silicon substrate on which a silicon epitaxial layer is grown is provided. Sacrificial structures on the substrate are formed from the epitaxial layer. A blanket silicon layer is formed over the sacrificial structures and exposed substrate portions, the blanket silicon layer having upper and lower portions of uniform thickness and intermediate portions interposed between the upper and lower portions of non-uniform thickness and having an angle of formation. An array of semiconducting fins is formed from the blanket silicon layer and a non-conformal layer formed over the blanket layer. The sacrificial structures are removed and the resulting void filled with isolation structures under the channel regions. Source and drain are formed in the source/drain regions during a fin merge of the FinFET.

Abstract translation: 改进的鳍状场效应晶体管（FinFET）器件及其制造方法。 一方面，一种用于制造FinFET器件的方法包括：提供生长有硅外延层的硅衬底。 衬底上的牺牲结构由外延层形成。 在牺牲结构和暴露的衬底部分之上形成覆盖硅层，所述覆盖硅层具有均匀厚度的上部和下部，并且中间部分插入在不均匀厚度的上部和下部之间并且具有形成角度。 半导体散热片阵列由覆盖硅层和覆盖层上形成的非共形层形成。 去除牺牲结构，并且在通道区域下填充隔离结构的所得空隙。 在FinFET的鳍合并期间，在源极/漏极区域中形成源极和漏极。

公开(公告)号：US20140239395A1

公开(公告)日：2014-08-28

申请号：US13775946

申请日：2013-02-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMicroelectronics, Inc.

Inventor： Veeraraghavan S. Basker ,  Qing Liu ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L29/165 ,  H01L29/456 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for forming contacts in a semiconductor device includes forming a plurality of substantially parallel semiconductor fins on a dielectric layer of a substrate having a gate structure formed transversely to a longitudinal axis of the fins. The fins are merged by epitaxially growing a crystalline material between the fins. A field dielectric layer is deposited over the fins and the crystalline material. Trenches that run transversely to the longitudinal axis of the fins are formed to expose the fins in the trenches. An interface layer is formed over portions of the fins exposed in the trenches. Contact lines are formed in the trenches that contact a top surface of the interface layer on the fins and at least a portion of side surfaces of the interface layer on the fins.

Abstract translation: 一种用于在半导体器件中形成触点的方法包括在具有横向于鳍的纵向轴线形成的栅极结构的基底的介电层上形成多个基本上平行的半导体鳍。 翅片通过在翅片之间外延生长结晶材料而合并。 场致电介质层沉积在鳍片和结晶材料上。 形成横向于翅片的纵向轴线的沟槽以暴露沟槽中的翅片。 界面层形成在暴露在沟槽中的翅片的部分上。 接触线形成在与鳍片上的界面层的顶表面和鳍片上界面层的至少一部分侧表面接触的沟槽中。

公开(公告)号：US20140099773A1

公开(公告)日：2014-04-10

申请号：US14096515

申请日：2013-12-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS, INC.

Inventor： Bruce B. Doris ,  Shom Ponoth ,  Prasanna Khare ,  Qing Liu ,  Nicolas Loubet ,  Maud Vinet

IPC: H01L21/768 ,  H01L21/762

CPC classification number: H01L21/76879 ,  H01L21/0217 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76897 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/66628 ,  H01L29/78609

Abstract: A shallow trench is formed to extend into a handle substrate of a semiconductor-on-insulator (SOI) layer. A dielectric liner stack of a dielectric metal oxide layer and a silicon nitride layer is formed in the shallow trench, followed by deposition of a shallow trench isolation fill portion. The dielectric liner stack is removed from above a top surface of a top semiconductor portion, followed by removal of a silicon nitride pad layer and an upper vertical portion of the dielectric metal oxide layer. A divot laterally surrounding a stack of a top semiconductor portion and a buried insulator portion is filled with a silicon nitride portion. Gate structures and source/drain structures are subsequently formed. The silicon nitride portion or the dielectric metal oxide layer functions as a stopping layer during formation of source/drain contact via holes, thereby preventing electrical shorts between source/drain contact via structures and the handle substrate.