公开(公告)号：US20140355352A1

公开(公告)日：2014-12-04

申请号：US14462078

申请日：2014-08-18

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C16/04

CPC classification number: G11C16/0483 ,  G11C11/5642 ,  G11C16/24 ,  G11C16/26

Abstract: Various embodiments comprise apparatuses and methods including a three-dimensional memory apparatus having upper strings and lower strings. The upper strings can include a first string of memory cells and a second string of memory cells arranged substantially parallel and adjacent to one another. The lower strings can include a third string of memory cells and a fourth string of memory cells arranged substantially parallel and adjacent to one another. The strings can each have a separate sense amplifier coupled thereto. The first and third strings and the second and fourth strings can be configured to be respectively coupled in series with each other during a read operation. Additional apparatuses and methods are described.

Abstract translation: 各种实施例包括具有上弦和下弦的三维存储装置的装置和方法。 上部串可以包括第一串存储器单元和基本上平行并彼此相邻布置的第二存储单元串。 较低的串可以包括第三串存储器单元和基本上平行并彼此相邻布置的第四串存储单元。 串可以各自具有耦合到其上的单独的读出放大器。 第一和第三串以及第二和第四串可以被配置为在读取操作期间彼此串联耦合。 描述附加的装置和方法。

公开(公告)号：US20140334219A1

公开(公告)日：2014-11-13

申请号：US14444589

申请日：2014-07-28

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C5/06

CPC classification number: G11C5/063 ,  G11C5/025 ,  H01L27/11556 ,  H01L27/11582

Abstract: Some embodiments include apparatuses and methods having a first set of data lines, a second set of data lines, and memory cells located in different levels of the apparatus. In at least one of such embodiments, the memory cells can be arranged in memory cell strings between the first and second set of data lines. Other embodiments including additional apparatuses and methods are described.

Abstract translation: 一些实施例包括具有第一组数据线，第二组数据线以及位于该装置的不同级别的存储单元的装置和方法。 在这样的实施例中的至少一个中，存储器单元可以被布置在第一和第二组数据线之间的存储单元串中。 描述包括附加装置和方法的其他实施例。

公开(公告)号：US08780638B2

公开(公告)日：2014-07-15

申请号：US13971626

申请日：2013-08-20

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C11/34

CPC classification number: G11C16/26 ,  G11C7/00 ,  G11C16/0408 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3459

Abstract: Embodiments are provided that include a method including providing a first pulsed gate signal to a selected memory cell, wherein the pulsed gate signal alternates between a first voltage level and a second voltage level during a time period and sensing a data line response to determine data stored on the selected memory of cells. Further embodiments provide a system including a memory device, having a regulator circuit coupled to a plurality of access lines of a NAND memory cell, and a switching circuit configured to sequentially bias at least one of the plurality of the access lines between a first voltage level and a second voltage level based on an input signal.

Abstract translation: 提供的实施例包括一种方法，包括向所选择的存储单元提供第一脉冲栅极信号，其中脉冲栅极信号在一段时间段内在第一电压电平和第二电压电平之间交替并感测数据线响应以确定存储的数据 在选定的单元格内存上。 另外的实施例提供一种包括存储器件的系统，该存储器件具有耦合到NAND存储器单元的多个访问线路的调节器电路，以及切换电路，被配置为顺序地将多个接入线路中的至少一个在第一电压电平 以及基于输入信号的第二电压电平。