公开(公告)号：US11532512B2

公开(公告)日：2022-12-20

申请号：US17062822

申请日：2020-10-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L21/76 ,  H01L21/768 ,  H01L23/485 ,  H01L29/417 ,  H01L23/522 ,  H01L23/528 ,  H01L29/66 ,  H01L29/78 ,  H01L23/532

Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a first metal layer formed over a substrate and a dielectric layer formed over the first metal layer. The semiconductor device structure further includes an adhesion layer formed in the dielectric layer and over the first metal layer and a second metal layer formed in the dielectric layer. The second metal layer is electrically connected to the first metal layer, and a portion of the adhesion layer is formed between the second metal layer and the dielectric layer. The adhesion layer includes a first portion lining with a top portion of the second metal layer, and the first portion has an extending portion along a vertical direction.

公开(公告)号：US11527628B2

公开(公告)日：2022-12-13

申请号：US17038114

申请日：2020-09-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L21/76 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L21/265 ,  H01L21/324 ,  H01L21/768 ,  H01L21/285

Abstract: A semiconductor device and method of manufacture are provided. A source/drain region is formed next to a spacer, which is adjacent to a gate electrode. An implantation is performed through an implantation mask into the source/drain region as well as the first spacer, forming an implantation region within the spacer.

公开(公告)号：US20220165865A1

公开(公告)日：2022-05-26

申请号：US17671230

申请日：2022-02-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Po-Chi Wu ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78

Abstract: A method includes forming a first active fin structure and a second active fin structure on a substrate. A dummy fin structure is formed on the substrate, the dummy fin structure being interposed between the first active fin structure and the second active fin structure. The dummy fin structure is removed to expose a first portion of the substrate, the first portion of the substrate being disposed directly below the dummy fin structure. A plurality of protruding features is formed on the first portion of the substrate. A shallow trench isolation (STI) region is formed over the first portion of the substrate, the STI region covering the plurality of protruding features, at least a portion of the first active fin structure and at least a portion of the second active fin structure extending above a topmost surface of the STI region.

公开(公告)号：US11276578B2

公开(公告)日：2022-03-15

申请号：US17018479

申请日：2020-09-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chang-Yin Chen ,  Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L21/308 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L23/31 ,  H01L29/66

Abstract: A first semiconductor fin and a second semiconductor fin are disposed over a substrate. The second semiconductor fin and the first semiconductor fin are aligned substantially along a same line and spaced apart from each other. The first semiconductor fin has a first end portion, the second semiconductor fin has a second end portion, and an end sidewall of the first end portion and is spaced apart from an end sidewall of the second end portion. The gate structure extends substantially perpendicularly to the first semiconductor fin. When viewed from above, the gate structure overlaps with the first end portion of the first semiconductor fin. When viewed from above, the end sidewall of the first end portion of the first semiconductor fin facing the end sidewall of the second end portion of the second semiconductor fin has a re-entrant profile.

公开(公告)号：US11189728B2

公开(公告)日：2021-11-30

申请号：US16562406

申请日：2019-09-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chang-Yin Chen ,  Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/08

Abstract: A semiconductor device includes an isolation insulating layer disposed over a substrate, a semiconductor fin disposed over the substrate, an upper portion of the semiconductor fin protruding from the isolation insulating layer and a lower portion of the semiconductor fin being embedded in the isolation insulating layer, a gate structure disposed over the upper portion of the semiconductor fin and including a gate dielectric layer and a gate electrode layer, gate sidewall spacers disposed over opposing side faces of the gate structure, and a source/drain epitaxial layer. The upper portion of the semiconductor fin includes a first epitaxial growth enhancement layer made of a semiconductor material different from a remaining part of the semiconductor fin. The first epitaxial growth enhancement layer is in contact with the source/drain epitaxial layer. The gate dielectric layer covers the upper portion of the semiconductor fin including the first epitaxial growth enhancement layer.

公开(公告)号：US11158545B2

公开(公告)日：2021-10-26

申请号：US16452101

申请日：2019-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Yin Chen ,  Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L21/306 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/8234

Abstract: A method for fabricating a semiconductor device includes providing a structure having two fins over a substrate, lower portions of the fins being separated by an isolation structure, a dummy gate structure over the fins, and source/drain features over the fins on both sides of the dummy gate structure; forming a trench in the dummy gate structure between the two fins, where forming the trench removes a portion of the isolation structure; forming a dielectric layer in the trench, where a bottom surface of the dielectric layer extends below a top surface of the isolation structure; and replacing the dummy gate structure with one high-k metal gate structure formed over one of the fins and another high-k metal gate structure formed over the other of the fins.

公开(公告)号：US11120974B2

公开(公告)日：2021-09-14

申请号：US16908214

申请日：2020-06-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chang-Yin Chen ,  Tung-Wen Cheng ,  Che-Cheng Chang ,  Jr-Jung Lin ,  Chih-Han Lin

IPC: H01J37/32 ,  H01L21/8234 ,  H01L21/3213 ,  H01L29/66 ,  H01L29/78 ,  H01L21/67

Abstract: A dry etching apparatus includes a process chamber, a stage, a gas supply device and a plasma generating device. The stage is in the process chamber and is configured to support a wafer, wherein the wafer has a center region and a periphery region surrounding the center region. The gas supply device is configured to supply a first flow of an etching gas to the center region and supply a second flow of the etching gas to the periphery region. The plasma generating device is configured to generate plasma from the etching gas.

公开(公告)号：US20210257362A1

公开(公告)日：2021-08-19

申请号：US17313297

申请日：2021-05-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Han Lin ,  Che-Cheng Chang ,  Horng-Huei Tseng

IPC: H01L27/088 ,  H01L21/8234

Abstract: An exemplary semiconductor device includes first spacers disposed along sidewalls of a first gate structure and second spacers disposed along sidewalls of a second gate structure. A source/drain region is disposed between the first gate structure and the second gate structure. A first ILD layer is disposed between the first spacers and the second spacers. A portion of the first ILD layer has a first recessed upper surface. A dielectric layer is disposed over the first spacers, the second spacers, and the first recessed upper surface of the first ILD layer. A portion of the dielectric layer has a second recessed upper surface that is disposed over the portion of the first ILD layer having the first recessed upper surface. A second ILD layer is disposed over the dielectric layer. A contact extends through the second ILD layer, the dielectric layer, and the first ILD layer to the source/drain region.

公开(公告)号：US11075112B2

公开(公告)日：2021-07-27

申请号：US15851661

申请日：2017-12-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L21/768 ,  H01L23/485 ,  H01L23/532

Abstract: A method includes depositing a first dielectric structure over a non-insulator structure, removing a portion of the first dielectric structure to form a via opening, filling the via opening with a dummy structure, depositing a second dielectric structure over the dummy structure, etching a portion of the second dielectric structure to form a trench over the dummy structure, removing the dummy structure from the via opening, and filling the trench opening and the via opening with a conductive structure, wherein the conductive structure is electrically connected to the non-insulator structure.

公开(公告)号：US11043593B2

公开(公告)日：2021-06-22

申请号：US16594237

申请日：2019-10-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Yen Yu ,  Che-Cheng Chang ,  Tung-Wen Cheng ,  Zhe-Hao Zhang ,  Bo-Feng Young

IPC: H01L29/78 ,  H01L29/165 ,  H01L21/02 ,  H01L21/84 ,  H01L27/12 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/267

Abstract: A semiconductor device includes a Fin FET device. The Fin FET device includes a first fin structure extending in a first direction and protruding from an isolation insulating layer, a first gate stack including a first gate electrode layer and a first gate dielectric layer, covering a portion of the first fin structure and extending in a second direction perpendicular to the first direction, and a first source and a first drain, each including a first stressor layer disposed over the first fin structure. The first fin structure and the isolation insulating layer are disposed over a substrate. A height Ha of an interface between the first fin structure and the first stressor layer measured from the substrate is greater than a height Hb of a lowest height of the isolation insulating layer measured from the substrate.