公开(公告)号：US20240274691A1

公开(公告)日：2024-08-15

申请号：US18651757

申请日：2024-05-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chi Wu ,  Chai-Wei Chang ,  Kuo-Hui Chang ,  Yi-Cheng Chao

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/66553 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/4966

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a gate stack over a semiconductor substrate and a cap element over the gate stack. The cap element has an upper portion and a lower portion, and the upper portion is wider than the lower portion. The semiconductor device structure also includes a spacer element over a sidewall of the cap element and a sidewall of the gate stack.

公开(公告)号：US11784242B2

公开(公告)日：2023-10-10

申请号：US17853104

申请日：2022-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Po-Chi Wu ,  Che-Cheng Chang

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/3065 ,  H01L29/10 ,  H01L29/165

CPC classification number: H01L29/66818 ,  H01L21/3065 ,  H01L29/1037 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7848 ,  H01L29/165

Abstract: A manufacturing process and device are provided in which a first opening in formed within a substrate. The first opening is reshaped into a second opening using a second etching process. The second etching process is performed with a radical etch in which neutral ions are utilized. As such, substrate push is reduced.

公开(公告)号：US20220359726A1

公开(公告)日：2022-11-10

申请号：US17872562

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Po-Chi Wu ,  Chai-Wei Chang ,  Kuo-Hui Chang ,  Yi-Cheng Chao

IPC: H01L29/66 ,  H01L29/78

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a gate stack over a semiconductor substrate and a cap element over the gate stack. The cap element has an upper portion and a lower portion, and the upper portion is wider than the lower portion. The semiconductor device structure also includes a spacer element over a sidewall of the cap element and a sidewall of the gate stack.

公开(公告)号：US11387365B2

公开(公告)日：2022-07-12

申请号：US16837211

申请日：2020-04-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Yen Yu ,  Po-Chi Wu ,  Yueh-Chun Lai

IPC: H01L29/78 ,  H01L21/285 ,  H01L21/3065 ,  H01L21/764 ,  H01L29/06 ,  H01L29/08 ,  H01L29/45 ,  H01L29/66 ,  H01L21/762 ,  H01L29/165 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092

Abstract: In a method of manufacturing a semiconductor device including a Fin FET, a fin structure extending in a first direction is formed over a substrate. An isolation insulating layer is formed over the substrate so that an upper portion of the fin structure is exposed from the isolation insulating layer. A gate structure extending in a second direction crossing the first direction is formed over a part of the fin structure. A fin mask layer is formed on sidewalls of a source/drain region of the fin structure. The source/drain region of the fin structure is recessed. An epitaxial source/drain structure is formed over the recessed fin structure. In the recessing the source/drain region of the fin structure, a plasma process combining etching and deposition processes is used to form a recess having a rounded corner shape in a cross section along the second direction.

公开(公告)号：US11145510B2

公开(公告)日：2021-10-12

申请号：US16666218

申请日：2019-10-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Po-Chi Wu ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L27/12 ,  H01L29/06 ,  H01L21/225 ,  H01L29/78 ,  H01L29/66 ,  H01L29/36 ,  H01L21/84 ,  H01L21/8234 ,  H01L27/088

Abstract: A semiconductor device includes a substrate, a FinFET, and an insulating structure. The FinFET includes a fin, a gate electrode, and a gate dielectric layer. The fin is over the substrate. The gate electrode is over the fin. The gate dielectric layer is between the gate electrode and the fin. The insulating structure is over the substrate, adjacent the fin, and has a top surface lower than a top surface of the fin. The top surface of the insulating structure has opposite first and second edge portions and an intermediate portion between the first and second edge portions. The first edge portion of the top surface of the insulating structure is lower than the intermediate portion of the top surface of the insulating structure.

公开(公告)号：US10411113B2

公开(公告)日：2019-09-10

申请号：US14818965

申请日：2015-08-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Po-Chi Wu ,  Chai-Wei Chang ,  Kuo-Hui Chang ,  Yi-Cheng Chao

IPC: H01L29/49 ,  H01L29/66 ,  H01L29/78

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a gate stack over a semiconductor substrate and a cap element over the gate stack. The cap element has an upper portion and a lower portion, and the upper portion is wider than the lower portion. The semiconductor device structure also includes a spacer element over a sidewall of the cap element and a sidewall of the gate stack.

公开(公告)号：US09818841B2

公开(公告)日：2017-11-14

申请号：US14713517

申请日：2015-05-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chai-Wei Chang ,  Che-Cheng Chang ,  Po-Chi Wu ,  Yi-Cheng Chao

IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/3205 ,  H01L29/76 ,  H01L27/088 ,  H01L29/66 ,  H01L21/308 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L29/66545 ,  H01L21/3081 ,  H01L29/42356 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a fin structure formed over a substrate and a gate structure formed across the fin structure. In addition, the gate structure includes a gate dielectric layer formed over the substrate and a work function metal layer formed over the gate dielectric layer. The gate structure further includes a gate electrode layer formed over the work function metal layer. In addition, a top surface of the gate electrode layer is located at a position that is higher than that of a top surface of the gate dielectric layer, and the top surface of the gate dielectric layer is located at a position that is higher than that of a top surface of the work function layer.

公开(公告)号：US09818648B2

公开(公告)日：2017-11-14

申请号：US15236765

申请日：2016-08-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD

Inventor： Yi-Cheng Chao ,  Chai-Wei Chang ,  Po-Chi Wu ,  Jung-Jui Li

IPC: H01L21/00 ,  H01L27/00 ,  H01L29/00 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L21/308 ,  H01L21/762

CPC classification number: H01L21/823431 ,  H01L21/3081 ,  H01L21/76224 ,  H01L21/823456 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0642 ,  H01L29/0657 ,  H01L29/6681

Abstract: Methods for forming the fin field effect transistor (FinFET) device structure are provided. The method includes forming first fin structures and second fin structures on a first region and a second region of a substrate, respectively, and a number of the first fin structures is greater than a number of the second fin structures. The method also includes forming a sacrificial layer on the first fin structures and the second fin structures and performing an etching process to the sacrificial layer to form an isolation structure on the substrate.

公开(公告)号：US09786505B2

公开(公告)日：2017-10-10

申请号：US14984555

申请日：2015-12-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Po-Chi Wu ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L29/78 ,  H01L29/36 ,  H01L29/06 ,  H01L21/225 ,  H01L29/66

CPC classification number: H01L21/2253 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/36 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor structure includes a substrate, at least one active semiconductor fin, at least one insulating structure, a gate electrode, and a gate dielectric. The active semiconductor fin is disposed on the substrate. The insulating structure is disposed on the substrate and adjacent to the active semiconductor fin. A top surface of the insulating structure is non-concave and is lower than a top surface of the active semiconductor fin. The gate electrode is disposed over the active semiconductor fin. The gate dielectric is disposed between the gate electrode and the active semiconductor fin.

公开(公告)号：US20230119022A1

公开(公告)日：2023-04-20

申请号：US18067970

申请日：2022-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chi Wu ,  Chai-Wei Chang ,  Jung Jui Li ,  Ya-Lan Chang ,  Yi-Cheng Chao

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8238

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a substrate. The dielectric layer has a trench passing through the dielectric layer. The method includes forming a gate stack in the trench. The method includes performing a hydrogen-containing plasma process over the gate stack. The method includes removing a top portion of the gate stack to form a first recess surrounded by the gate stack and the dielectric layer. The method includes forming a cap layer in the first recess to fill the first recess.