公开(公告)号：US11842932B2

公开(公告)日：2023-12-12

申请号：US17739899

申请日：2022-05-09

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chang-Yin Chen ,  Che-Cheng Chang ,  Chih-Han Lin

IPC分类号： H01L29/49 ,  H01L29/423 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/51 ,  H01L21/308 ,  H01L27/092 ,  H01L29/10 ,  H01L21/306 ,  H01L21/3065

CPC分类号： H01L21/82385 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/30608 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/1033 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795

摘要： A method includes providing a substrate having a channel region, forming a gate stack layer over the channel region, forming a patterned hard mask over the gate stack layer, etching a top portion of the gate stack layer through openings in the patterned hard mask with a first etchant, etching a middle portion and a bottom portion of the gate stack layer with a second etchant that includes a passivating gas. A gate stack is formed with a passivation layer deposited on sidewalls of the gate stack. The method also includes etching the gate stack with a third etchant, thereby removing a bottom portion of the passivation layer and recessing a bottom portion of the gate stack.

公开(公告)号：US11342458B2

公开(公告)日：2022-05-24

申请号：US17080084

申请日：2020-10-26

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Che-Cheng Chang ,  Tung-Wen Cheng ,  Chang-Yin Chen ,  Mu-Tsang Lin

IPC分类号： H01L21/02 ,  H01L29/78 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3213 ,  H01L29/423 ,  H01L29/08 ,  H01L29/49 ,  H01L29/165 ,  H01L29/66 ,  H01L29/51

摘要： A semiconductor structure and a method of fabricating the semiconductor structure are provided. The semiconductor structure includes a substrate; a metal gate structure on the substrate; and a spacer next to the metal gate structure having a skirting part extending into the metal gate structure and contacting the substrate. The metal gate structure includes a high-k dielectric layer and a metal gate electrode on the high-k dielectric layer.

公开(公告)号：US11309189B2

公开(公告)日：2022-04-19

申请号：US16947396

申请日：2020-07-30

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chang-Yin Chen ,  Chai-Wei Chang ,  Chia-Yang Liao ,  Bo-Feng Young

IPC分类号： H01L29/66 ,  H01L21/311 ,  H01L29/78 ,  H01L29/423 ,  H01L21/28 ,  H01L21/3213

摘要： A FinFET device structure and method for forming the same are provided. The fin field effect transistor (FinFET) device structure includes a fin structure formed over a substrate and a gate structure traversing over the fin structure. The gate structure includes a gate electrode layer which includes an upper portion above the fin structure and a lower portion below the fin structure. The upper portion has a top surface with a first width, the lower portion has a bottom surface with a second width, and the first width is greater than the second width.

公开(公告)号：US20210074591A1

公开(公告)日：2021-03-11

申请号：US17099613

申请日：2020-11-16

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chang-Yin Chen ,  Che-Cheng Chang ,  Chih-Han Lin

IPC分类号： H01L21/8238 ,  H01L29/66 ,  H01L29/51 ,  H01L29/49 ,  H01L21/308 ,  H01L27/092 ,  H01L29/10 ,  H01L21/306 ,  H01L21/3065

摘要： A method includes providing a structure having a substrate and a fin protruding from the substrate, forming a gate stack layer over the fin, and patterning the gate stack layer in forming a gate stack. The patterning of the gate stack layer simultaneously forms a passivation layer on sidewall surfaces of the gate stack. The method also includes removing a bottom portion of the passivation layer, thereby exposing a bottom portion of the gate stack, while a top portion of the passivation layer remains. The method further includes laterally etching the bottom portion of the gate stack, thereby shrinking a width of the bottom portion of the gate stack.

公开(公告)号：US20210036148A1

公开(公告)日：2021-02-04

申请号：US17074532

申请日：2020-10-19

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chang-Yin Chen ,  Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L29/49 ,  H01L29/423 ,  H01L21/3213 ,  H01L21/66 ,  H01L21/8234 ,  H01L21/67

摘要： A FinFET structure with a gate structure having two notch features therein and a method of forming the same is disclosed. The FinFET notch features ensure that sufficient spacing is provided between the gate structure and source/drain regions of the FinFET to avoid inadvertent shorting of the gate structure to the source/drain regions. Gate structures of different sizes (e.g., different gate widths) and of different pattern densities can be provided on a same substrate and avoid inadvertent of shorting the gate to the source/drain regions through application of the notched features.

公开(公告)号：US12125891B2

公开(公告)日：2024-10-22

申请号：US17244430

申请日：2021-04-29

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wei-Liang Lu ,  Chang-Yin Chen ,  Chih-Han Lin ,  Chia-Yang Liao

IPC分类号： H01L29/49 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/4983 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823821 ,  H01L21/823864 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

摘要： A semiconductor device and methods of fabricating the same are disclosed. The semiconductor device includes a substrate, a fin structure with a fin top surface disposed on the substrate, a source/drain (S/D) region disposed on the fin structure, a gate structure disposed on the fin top surface, and a gate spacer with first and second spacer portions disposed between the gate structure and the S/D region. The first spacer portion extends above the fin top surface and is disposed along a sidewall of the gate structure. The second spacer portion extends below the fin top surface and is disposed along a sidewall of the S/D region.

公开(公告)号：US20230114917A1

公开(公告)日：2023-04-13

申请号：US18061862

申请日：2022-12-05

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chang-Yin Chen ,  Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L29/49 ,  H01L29/423 ,  H01L21/3213 ,  H01L21/66 ,  H01L21/8234 ,  H01L21/67

摘要： A FinFET structure with a gate structure having two notch features therein and a method of forming the same is disclosed. The FinFET notch features ensure that sufficient spacing is provided between the gate structure and source/drain regions of the FinFET to avoid inadvertent shorting of the gate structure to the source/drain regions. Gate structures of different sizes (e.g., different gate widths) and of different pattern densities can be provided on a same substrate and avoid inadvertent of shorting the gate to the source/drain regions through application of the notched features.

公开(公告)号：US11522084B2

公开(公告)日：2022-12-06

申请号：US17074532

申请日：2020-10-19

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chang-Yin Chen ,  Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC分类号： H01L21/82 ,  H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L29/49 ,  H01L29/423 ,  H01L21/3213 ,  H01L21/66 ,  H01L21/8234 ,  H01L21/67 ,  G01N21/88

摘要： A FinFET structure with a gate structure having two notch features therein and a method of forming the same is disclosed. The FinFET notch features ensure that sufficient spacing is provided between the gate structure and source/drain regions of the FinFET to avoid inadvertent shorting of the gate structure to the source/drain regions. Gate structures of different sizes (e.g., different gate widths) and of different pattern densities can be provided on a same substrate and avoid inadvertent of shorting the gate to the source/drain regions through application of the notched features.

公开(公告)号：US10692701B2

公开(公告)日：2020-06-23

申请号：US15460771

申请日：2017-03-16

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Chang-Yin Chen ,  Tung-Wen Cheng ,  Che-Cheng Chang ,  Jr-Jung Lin ,  Chih-Han Lin

IPC分类号： H01L21/8234 ,  H01J37/32 ,  H01L21/3213 ,  H01L29/66 ,  H01L29/78 ,  H01L21/67

摘要： A dry etching apparatus includes a process chamber, a stage, a gas supply device and a plasma generating device. The stage is in the process chamber and is configured to support a wafer, wherein the wafer has a center region and a periphery region surrounding the center region. The gas supply device is configured to supply a first flow of an etching gas to the center region and supply a second flow of the etching gas to the periphery region. The plasma generating device is configured to generate plasma from the etching gas.

公开(公告)号：US20200006148A1

公开(公告)日：2020-01-02

申请号：US16161833

申请日：2018-10-16

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chang-Yin Chen ,  Che-Cheng Chang ,  Chih-Han Lin

IPC分类号： H01L21/8238 ,  H01L29/66 ,  H01L29/51 ,  H01L29/49 ,  H01L27/092 ,  H01L29/10 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308

摘要： A method includes providing a structure having a first region and a second region, the first region including a first channel region, the second region including a second channel region; forming a gate stack layer over the first and second regions; patterning the gate stack layer, thereby forming a first gate stack over the first channel region and a second gate stack over the second channel region; and laterally etching bottom portions of the first and second gate stacks by applying different etchant concentrations to the first and second regions simultaneously, thereby forming notches at the bottom portions of the first and second gate stacks.