公开(公告)号：US11189728B2

公开(公告)日：2021-11-30

申请号：US16562406

申请日：2019-09-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chang-Yin Chen ,  Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/08

Abstract: A semiconductor device includes an isolation insulating layer disposed over a substrate, a semiconductor fin disposed over the substrate, an upper portion of the semiconductor fin protruding from the isolation insulating layer and a lower portion of the semiconductor fin being embedded in the isolation insulating layer, a gate structure disposed over the upper portion of the semiconductor fin and including a gate dielectric layer and a gate electrode layer, gate sidewall spacers disposed over opposing side faces of the gate structure, and a source/drain epitaxial layer. The upper portion of the semiconductor fin includes a first epitaxial growth enhancement layer made of a semiconductor material different from a remaining part of the semiconductor fin. The first epitaxial growth enhancement layer is in contact with the source/drain epitaxial layer. The gate dielectric layer covers the upper portion of the semiconductor fin including the first epitaxial growth enhancement layer.

公开(公告)号：US11158545B2

公开(公告)日：2021-10-26

申请号：US16452101

申请日：2019-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Yin Chen ,  Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L21/306 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/8234

Abstract: A method for fabricating a semiconductor device includes providing a structure having two fins over a substrate, lower portions of the fins being separated by an isolation structure, a dummy gate structure over the fins, and source/drain features over the fins on both sides of the dummy gate structure; forming a trench in the dummy gate structure between the two fins, where forming the trench removes a portion of the isolation structure; forming a dielectric layer in the trench, where a bottom surface of the dielectric layer extends below a top surface of the isolation structure; and replacing the dummy gate structure with one high-k metal gate structure formed over one of the fins and another high-k metal gate structure formed over the other of the fins.

公开(公告)号：US20210313450A1

公开(公告)日：2021-10-07

申请号：US17345188

申请日：2021-06-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Han Lin ,  Ming-Ching Chang ,  Chao-Cheng Chen

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/423

Abstract: A semiconductor device includes a fin extending from a substrate, a gate stack over and along a sidewall of the fin, a spacer along a first sidewall of the gate stack and the sidewall of the fin, a dummy gate material along the sidewall of the fin, wherein the dummy gate material is between the spacer and the gate stack, and a first epitaxial source/drain region in the fin and adjacent the gate stack.

公开(公告)号：US11120974B2

公开(公告)日：2021-09-14

申请号：US16908214

申请日：2020-06-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chang-Yin Chen ,  Tung-Wen Cheng ,  Che-Cheng Chang ,  Jr-Jung Lin ,  Chih-Han Lin

IPC: H01J37/32 ,  H01L21/8234 ,  H01L21/3213 ,  H01L29/66 ,  H01L29/78 ,  H01L21/67

Abstract: A dry etching apparatus includes a process chamber, a stage, a gas supply device and a plasma generating device. The stage is in the process chamber and is configured to support a wafer, wherein the wafer has a center region and a periphery region surrounding the center region. The gas supply device is configured to supply a first flow of an etching gas to the center region and supply a second flow of the etching gas to the periphery region. The plasma generating device is configured to generate plasma from the etching gas.

公开(公告)号：US20210257362A1

公开(公告)日：2021-08-19

申请号：US17313297

申请日：2021-05-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Han Lin ,  Che-Cheng Chang ,  Horng-Huei Tseng

IPC: H01L27/088 ,  H01L21/8234

Abstract: An exemplary semiconductor device includes first spacers disposed along sidewalls of a first gate structure and second spacers disposed along sidewalls of a second gate structure. A source/drain region is disposed between the first gate structure and the second gate structure. A first ILD layer is disposed between the first spacers and the second spacers. A portion of the first ILD layer has a first recessed upper surface. A dielectric layer is disposed over the first spacers, the second spacers, and the first recessed upper surface of the first ILD layer. A portion of the dielectric layer has a second recessed upper surface that is disposed over the portion of the first ILD layer having the first recessed upper surface. A second ILD layer is disposed over the dielectric layer. A contact extends through the second ILD layer, the dielectric layer, and the first ILD layer to the source/drain region.

公开(公告)号：US11075112B2

公开(公告)日：2021-07-27

申请号：US15851661

申请日：2017-12-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L21/768 ,  H01L23/485 ,  H01L23/532

Abstract: A method includes depositing a first dielectric structure over a non-insulator structure, removing a portion of the first dielectric structure to form a via opening, filling the via opening with a dummy structure, depositing a second dielectric structure over the dummy structure, etching a portion of the second dielectric structure to form a trench over the dummy structure, removing the dummy structure from the via opening, and filling the trench opening and the via opening with a conductive structure, wherein the conductive structure is electrically connected to the non-insulator structure.

公开(公告)号：US20210143276A1

公开(公告)日：2021-05-13

申请号：US17120814

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/762 ,  H01L21/768 ,  H01L23/535 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66

Abstract: A representative method for manufacturing a semiconductor device (e.g., a fin field-effect transistor) includes the steps of forming a gate structure having a first lateral width, and forming a first via opening over the gate structure. The first via opening has a lowermost portion that exposes an uppermost surface of the gate structure. The lowermost portion of the first via opening has a second lateral width. A ratio of the second lateral width to the first lateral width is less than about 1.1. A source/drain (S/D) region is disposed laterally adjacent the gate structure. A contact feature is disposed over the S/D region. A second via opening extends to and exposes an uppermost surface of the contact feature. A bottommost portion of the second via opening is disposed above a topmost portion of the gate structure.

公开(公告)号：US11004846B2

公开(公告)日：2021-05-11

申请号：US16891992

申请日：2020-06-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Han Lin ,  Che-Cheng Chang ,  Horng-Huei Tseng

IPC: H01L27/088 ,  H01L21/8234

Abstract: An exemplary semiconductor device includes first spacers disposed along sidewalls of a first gate structure and second spacers disposed along sidewalls of a second gate structure. A source/drain region is disposed between the first gate structure and the second gate structure. A first ILD layer is disposed between the first spacers and the second spacers. A portion of the first ILD layer has a first recessed upper surface. A dielectric layer is disposed over the first spacers, the second spacers, and the first recessed upper surface of the first ILD layer. A portion of the dielectric layer has a second recessed upper surface that is disposed over the portion of the first ILD layer having the first recessed upper surface. A second ILD layer is disposed over the dielectric layer. A contact extends through the second ILD layer, the dielectric layer, and the first ILD layer to the source/drain region.

公开(公告)号：US10998226B2

公开(公告)日：2021-05-04

申请号：US16206768

申请日：2018-11-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/485

Abstract: A method of forming an interconnection structure includes following steps. A dielectric structure is deposited over a non-insulator structure. The dielectric structure is etched to form a via opening. A mask layer is formed over the dielectric structure. The mask layer is patterned. An anti-adhesion layer is deposited on a sidewall of the via opening after patterning the mask layer. The dielectric structure is etched to form a trench opening, wherein the patterned mask layer is used as an etch mask during forming the trench opening. A conductive structure is formed in the via opening and the trench opening.

公开(公告)号：US10777419B2

公开(公告)日：2020-09-15

申请号：US16243242

申请日：2019-01-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chang-Yin Chen ,  Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L21/308 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L23/31

Abstract: A fin strip is formed over a substrate using a hardmask. The fin strip includes a first portion and a second portion laterally adjoining the first portion. A BARC layer is formed to cover the fin strip over the substrate. A first etching operation is performed to remove a first portion of the BARC layer, so as to expose a portion of the hardmask where the first portion of the fin strip underlies. A coating layer is deposited over the portion of the hardmask and the BARC layer. A second etching operation is performed to remove a portion of the coating layer, the portion of the hardmask and a second portion of the BARC layer. A third etching operation is performed to remove the first portion of the fin strip and a remaining BARC layer, such that the second portion of the fin strip forms a plurality of semiconductor fins.