公开(公告)号：US20060084401A1

公开(公告)日：2006-04-20

申请号：US11294802

申请日：2005-12-06

Applicant: Armand Castillejo ,  Fabienne Rerat

Inventor： Armand Castillejo ,  Fabienne Rerat

IPC: H04B1/16

CPC classification number: H01F21/12 ,  H01F17/0006 ,  H01F2017/0046 ,  H01F2021/125 ,  H01L23/5227 ,  H01L23/66 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: An integrated circuit including a structure of inductances on a semiconductor substrate, intended for operating at frequencies greater than several hundreds of MHz, including a first inductance formed by a conductive track and having first and second terminals respectively connected to each of the two ends of the conductive track, including a second inductance formed by the conductive track between the second terminal and any intermediary point of the conductive track connected to a third terminal, said second and third terminals forming the two terminals of the second inductance, and means for setting the third terminal to high impedance when the first inductance is used.

公开(公告)号：US07029991B2

公开(公告)日：2006-04-18

申请号：US10312024

申请日：2001-06-21

Applicant: Vincent Le Goascoz ,  Herve Jaouen

Inventor： Vincent Le Goascoz ,  Herve Jaouen

IPC: H01L21/322

CPC classification number: H01L21/26533 ,  H01L21/76243

Abstract: The invention concerns a method comprising: 1) a first phase including steps which consist in forming in the upper part of a first initial semiconductor substrate a first layer of insulating material above a sectional plane of said first substrate, contacting the first layer of insulating material with the insulating upper part of a second initial substrate, so as to form a single layer of insulating material, a break at the sectional plane, so as to obtain an intermediate semiconductor substrate on the single insulating material layer; then, 2) in a second phase which consists in forming in the intermediate semiconductor substrate an additional insulating material layer adjacent to the single insulating material and topped with an upper layer of a final semiconductor substrate.

Abstract translation: 本发明涉及一种方法，包括：1）包括以下步骤的第一相：第一阶段，其包括在第一初始半导体衬底的上部形成在所述第一衬底的截面上方的第一绝缘材料层，与第一绝缘材料层接触 与第二初始衬底的绝缘上部形成单层绝缘材料，在截面上形成断裂，以在单个绝缘材料层上获得中间半导体衬底; 那么2）在第二阶段中，其包括在中间半导体衬底中形成与单个绝缘材料相邻的附加的绝缘材料层并且顶上最后的半导体衬底的上层。

公开(公告)号：US07015105B2

公开(公告)日：2006-03-21

申请号：US10169237

申请日：2001-10-26

Applicant: Laurence Boissonnet ,  Dominique Golanski ,  Bruno Rauber ,  Andre Granier

Inventor： Laurence Boissonnet ,  Dominique Golanski ,  Bruno Rauber ,  Andre Granier

IPC: H01L21/8234

CPC classification number: H01L27/088 ,  H01L21/26586 ,  H01L21/8234 ,  H01L29/6659

Abstract: A method of simultaneously fabricating a pair of insulated gate transistors respectively having a thin oxide and a thick oxide, and an integrated circuit including a pair of transistors of this kind. Forming low-doped NLDD areas of the thin oxide second transistor includes implanting a first dopant having a first concentration and implanting a second dopant having a second concentration lower than the first concentration. Forming low-doped areas NLDD of the first, thick oxide transistor includes only said implantation of the second dopant.

Abstract translation: 同时制造分别具有薄氧化物和厚氧化物的一对绝缘栅极晶体管的方法，以及包括这种一对晶体管的集成电路。 形成薄氧化物第二晶体管的低掺杂NLDD区域包括植入具有第一浓度的第一掺杂物并且注入具有低于第一浓度的第二浓度的第二掺杂剂。 形成第一厚氧化物晶体管的低掺杂区域NLDD仅包括第二掺杂剂的所述注入。

公开(公告)号：US20060050585A1

公开(公告)日：2006-03-09

申请号：US11083112

申请日：2005-03-17

Applicant: Jean Lasseuguette ,  Cyrille Dray ,  Sebastien Barasinski

Inventor： Jean Lasseuguette ,  Cyrille Dray ,  Sebastien Barasinski

IPC: G11C7/02

CPC classification number: G11C11/16 ,  G11C5/147 ,  H03F1/223 ,  H03F3/45188 ,  H03F2203/45248

Abstract: The invention relates to a device for setting up a write current on at least one write conducting line in an MRAM type integrated circuit memory, including a current mirror composed of a first stage acting as the reference regulated cascode stage receiving all or part of the write current on its input and a second stage acting as the copy regulated cascode stage copying the write current onto the write line.

公开(公告)号：US07003407B1

公开(公告)日：2006-02-21

申请号：US10399817

申请日：2000-10-23

Applicant: Ahmed Kari ,  Christophe Moreaux

Inventor： Ahmed Kari ,  Christophe Moreaux

IPC: G06F3/00

CPC classification number: G06K19/07 ,  G06K19/0723

Abstract: The invention concerns non-contact smart cards and, more particularly in such cards, a circuit for detecting data frames and providing them with a parallel format for their processing. The invention is characterised in that it consists in using the information contained in the first octets of the frame being currently received, thereby enabling to identify them as they are received and route them into registers (80). This is provided by a state machine (60) whereof the shift from one state to the other is switched by the circuitry (62, 76) output signals.

Abstract translation: 本发明涉及非接触式智能卡，更具体地说，涉及这种卡，用于检测数据帧并为它们提供用于其处理的并行格式的电路。 本发明的特征在于，它包括使用包含在当前接收到的帧的第一个八比特组中的信息，从而使得能够在它们被接收时识别它们，并将它们路由到寄存器（80）中。 这由状态机（60）提供，其中通过电路（62,76）切换从一个状态到另一状态的输出信号。

公开(公告)号：US20060026313A1

公开(公告)日：2006-02-02

申请号：US10531510

申请日：2002-10-29

Applicant: Laurent Regnier

Inventor： Laurent Regnier

IPC: G06F3/00

CPC classification number: G06F11/273 ,  G06F11/2236 ,  G06F11/3466

Abstract: The invention concerns a method for transmitting digital messages through a microprocessor monitoring circuit (18) of specific type and integrated to a microprocessor (12). Each message including an identifier and consisting of several groups of successive and juxtaposed bits divided into segments. The method consists in successively transmitting segments associated with a first group corresponding to the identifier and comprising a fixed number of bits; with second groups, at least one of the second group comprising a fixed number of bits depending on the type of monitoring circuit, the number of other second groups being independent of the type of monitoring circuit; with a third group comprising a number of bits greater than one: and with fourth groups comprising each a number of bits greater than one, the number of fourth groups depending on the identifier and on the type of monitoring circuit.

Abstract translation: 本发明涉及一种通过特定类型的微处理器监视电路（18）发送数字消息并集成到微处理器（12）的方法。 每个消息包括标识符并由被划分成段的连续和并置位的几组组成。 该方法包括连续地发送与对应于该标识符的第一组相关联的段并且包括固定数量的比特; 利用第二组，根据监视电路的类型，第二组中的至少一个包括固定位数，其他第二组的数量与监视电路的类型无关; 其中第三组包括大于1的位数，并且第四组包括大于1的位数，第四组的数量取决于标识符和监视电路的类型。

公开(公告)号：US06993313B2

公开(公告)日：2006-01-31

申请号：US09918792

申请日：2001-07-30

Applicant: Armand Castillejo ,  Fabienne Rerat

Inventor： Armand Castillejo ,  Fabienne Rerat

IPC: H04B1/28 ,  H04B1/18 ,  H05F5/00

CPC classification number: H01F21/12 ,  H01F17/0006 ,  H01F2017/0046 ,  H01F2021/125 ,  H01L23/5227 ,  H01L23/66 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: An integrated circuit including a structure of inductances on a semiconductor substrate, intended for operating at frequencies greater than several hundreds of MHz, including a first inductance formed by a conductive track and having first and second terminals respectively connected to each of the two ends of the conductive track, including a second inductance formed by the conductive track between the second terminal and any intermediary point of the conductive track connected to a third terminal, said second and third terminals forming the two terminals of the second inductance, and means for setting the third terminal to high impedance when the first inductance is used.

公开(公告)号：US20060018029A1

公开(公告)日：2006-01-26

申请号：US11187691

申请日：2005-07-22

Applicant: Emmanuelle Vigier-Blanc

Inventor： Emmanuelle Vigier-Blanc

IPC: G02B3/00

CPC classification number: H01L31/0203 ,  H01L27/14618 ,  H01L27/14627 ,  H01L31/0232 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An optical unit including a glass substrate supporting a diaphragm intended to receive a lens with a circular base, the surface of the diaphragm having one or several protruding elements for guiding the lens in horizontal positioning, and its manufacturing method.

Abstract translation: 一种光学单元，包括支撑用于接收具有圆形基底的透镜的光阑的玻璃基板，所述光阑的表面具有用于在水平定位中引导透镜的一个或多个突出元件及其制造方法。

公开(公告)号：US06989570B2

公开(公告)日：2006-01-24

申请号：US10405075

申请日：2003-03-31

Applicant: Thomas Skotnicki ,  Daniel Bensahel

Inventor： Thomas Skotnicki ,  Daniel Bensahel

IPC: H01L27/12

CPC classification number: H01L29/66651 ,  H01L29/0649 ,  H01L29/41783 ,  H01L29/66772 ,  H01L29/7842 ,  H01L29/78618 ,  H01L29/78639 ,  H01L29/78687

Abstract: A transistor is located on a base layer 1 resting on a semiconductor substrate SB and formed from a relaxed silicon-germanium layer, and includes, under the isolated gate 7, a first strained silicon layer 2 resting on the base layer 1, surmounted by a buried insulating layer 10, surmounted by a second strained silicon layer 4 extending between the source S and drain D regions.

Abstract translation: 晶体管位于沉积在半导体衬底SB上的基底层1上并由松弛的硅 - 锗层形成，并且在隔离栅极7下方包括搁置在基底层1上的第一应变硅层2， 掩埋绝缘层10，其由在源极S和漏极D区域之间延伸的第二应变硅层4所覆盖。

公开(公告)号：US20060008079A1

公开(公告)日：2006-01-12

申请号：US11175915

申请日：2005-07-06

Applicant: Joan Daemen ,  Pierre Guillemin ,  Claude Anguille ,  Michel Bardouillet ,  Pierre-Yvan Liardet ,  Yannick Teglia

Inventor： Joan Daemen ,  Pierre Guillemin ,  Claude Anguille ,  Michel Bardouillet ,  Pierre-Yvan Liardet ,  Yannick Teglia

IPC: H04K1/00

CPC classification number: G06F12/1408 ,  H04L9/065 ,  H04L2209/12

Abstract: A method and an element of ciphering by an integrated processor of data to be stored in a memory, including applying a ciphering algorithm which is a function of a key specific to the integrated circuit and of an initialization vector, and of memorizing at least the ciphered data, the initialization vector depending at least on the address of storage of the data in the memory.

Abstract translation: 一种由存储在存储器中的数据的集成处理器进行加密的方法和元件，包括应用作为集成电路特有的密钥和初始化向量的函数的加密算法，以及至少记忆密码 数据，初始化向量至少取决于存储器中数据的存储地址。