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公开(公告)号：US12153241B2
公开(公告)日：2024-11-26
申请号：US17877249
申请日：2022-07-29
Inventor： Hiroshi Ando , Kazuyuki Ishihara , Masatoshi Tsuji
Abstract: An optical member includes a light guide body. The light guide body has an incident surface on which an outside light is incident, a first surface having flat portions and prism portions, an incident light incident on the incident surface reaching the first surface for the first time, and a second surface arranged opposite to the flat portions. The flat portions totally reflect the incident light toward the second surface. The second surface totally reflects a reflected light reflected by the flat portion toward the first surface. The prism portion has an ejection surface to emit the incident light to outside.
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公开(公告)号：US12149053B2
公开(公告)日：2024-11-19
申请号：US18193980
申请日：2023-03-31
Applicant: DENSO CORPORATION , TOYOTA JIDOSHA KABUSHIKI KAISHA , MIRISE Technologies Corporation , QD LASER, Inc.
Inventor： Hitoshi Yamada , Yuki Kamata , Koichi Oyama , Yutaka Ohnishi , Kenichi Nishi , Keizo Takemasa
Abstract: In a semiconductor device, a quantum dot group includes a stack of plural quantum dot layers having different central wavelengths at which respective gains are maximum. A part of or all of the quantum dot layers are stacked so that the central wavelengths sequentially shifts along a stacking direction. The quantum dot group includes a longest wavelength layer group composed of some quantum dot layers including a longest wavelength layer having a longest central wavelength and at least one quantum dot layer stacked on the longest wavelength layer. The longest wavelength layer or the longest wavelength layer group has a larger gain at the central wavelength than the gain at the central wavelength of each of the other quantum dot layers.
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公开(公告)号：US12140740B2
公开(公告)日：2024-11-12
申请号：US17835029
申请日：2022-06-08
Inventor： Masatoshi Tsuji , Kodai Takeda , Hiroshi Ando
Abstract: An optical device introduces light from an outdoor view in a blind spot area hidden by an obstacle. The optical device includes a first reflector that reflects a part of light and transmits another part of the light, and a second reflector placed between a back surface of the first reflector and the obstacle and apart from the first reflector. The second reflector has a reflective surface that reflects light incident from the first reflector toward the first reflector. A light shield is placed at a front surface of the first reflector to block external light incident on and reflected from the front surface of the first reflector. The light shield includes light-shielding plates arranged at an interval in a vertical direction such that each light-shielding plate is horizontal. The first reflector is parallel to the reflective surface of the second reflector and tilted from a vertical axis.
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公开(公告)号：US20240304459A1
公开(公告)日：2024-09-12
申请号：US18420016
申请日：2024-01-23
Inventor： SHUHEI ICHIKAWA , HIROKI MIYAKE , TATSUJI NAGAOKA
IPC: H01L21/385 , H01L21/02
CPC classification number: H01L21/385 , H01L21/02233
Abstract: In a manufacturing method of a semiconductor device, a semiconductor substrate made of β-gallium oxide and having a first surface or a second surface in a range of 45 to 90° with respect to a (100) plane or to a (001) plane is prepared. The semiconductor substrate is placed on a susceptor in a chamber so that the second surface faces the susceptor. The chamber is sealed, and a heat treatment is performed. In the heat treatment, a temperature of the semiconductor substrate is increased and then decreased by heat transfer by adjusting a temperature of the susceptor. The sealing of the chamber is then released. In the heat treatment, the temperature of the semiconductor substrate is increased to 300° C. or more by increasing a temperature of the susceptor at a temperature increase rate of 100° C./min or less.
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公开(公告)号：US20240302597A1
公开(公告)日：2024-09-12
申请号：US18437287
申请日：2024-02-09
Inventor： Yuki KAMATA , Toshihiro ODA
CPC classification number: G02B6/305 , G02B6/036 , G02F1/0115
Abstract: A spot size converter includes: a first core layer extending in a first direction and stacked on a cladding layer in a second direction; and a second core layer spaced apart from the first core layer in a third direction. The first core layer has a flat shape in which a size in the second direction is smaller than a size in the third direction, and includes a first tapered portion in which a size thereof in the third direction decreases along an emission direction. A size of the second core layer in the second direction is larger than that of the first core layer in the second direction, and includes a second tapered portion in which a size thereof in the third direction increases along the emission direction. The second tapered portion is disposed to overlap the first tapered portion in the third direction.
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Patent Agency Ranking
256.发明公开公开(公告)号：US20240250164A1
公开(公告)日：2024-07-25
申请号：US18543719
申请日：2023-12-18
Inventor： Masahiro KUMITA , Katsumi SUZUKI , Takuji ARAUCHI , Jun SAITO
CPC classification number: H01L29/7805 , H01L21/02529 , H01L21/02576 , H01L21/0262 , H01L21/046 , H01L29/1608 , H01L29/66068 , H01L29/7813
Abstract: A diode has a semiconductor substrate made of silicon carbide. The semiconductor substrate includes a p-type first semiconductor region, a drift region below the first semiconductor region, and an n-type second semiconductor region below the drift region. The drift region has a plurality of p-type column regions and a plurality of n-type column regions alternately arranged in a lateral direction. The drift region includes a specific region distributed over the plurality of p-type column regions and the plurality of n-type column regions, at least at a part in a depth direction. The plurality of p-type column regions has an effective p-type impurity concentration that is lower in the specific region than in a portion around the specific region, and the plurality of n-type column regions has an effective n-type impurity concentration that is higher in the specific region than in a portion around the specific region.
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公开(公告)号：US12043918B2
公开(公告)日：2024-07-23
申请号：US17881255
申请日：2022-08-04
Inventor： Daisuke Uematsu
CPC classification number: C30B25/16 , C30B29/36 , G05B13/0265 , C30B23/00 , C30B23/02 , C30B23/025
Abstract: A control device has a learning model that outputs an estimated value of a second physical quantity that is unobservable under a condition of manufacturing a SiC crystal, from a first physical quantity that is observable under the condition of manufacturing the SiC crystal. The control device generates a basic learning model by mechanical learning using, as teacher data, a simulation result of a simulation model based on structural data of a SiC crystal manufacturing apparatus. The control device acquires measured values of the first physical quantity and the second physical quantity measured under a condition that the SiC crystal is unable to be manufactured while the second physical quantity is observable, and generates the learning model that corrects an output of the basic learning model based on the measured values.
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公开(公告)号：US20240213341A1
公开(公告)日：2024-06-27
申请号：US18524195
申请日：2023-11-30
Inventor： Hitoshi FUJIOKA
IPC: H01L29/423 , H01L29/66 , H01L29/78
CPC classification number: H01L29/4236 , H01L29/66734 , H01L29/7813
Abstract: A semiconductor device includes a semiconductor layer formed with trenches, and trench gates correspondingly disposed in the trenches. The trenches extend in a first direction, and are arranged spaced apart from each other in a second direction orthogonal to the first direction. The trenches include an inner trench located between end trenches in the second direction. The inner trench has end side walls opposite in the first direction, and longitudinal side walls between the end side walls. The end side walls have a surface roughness larger than that of intermediate portions of the longitudinal side walls, the intermediate portions being at an intermediate position in the first direction. An insulating film disposed in the inner trench has a larger thickness on at least one of the end side walls than on at least one of intermediate portions of the longitudinal side walls.
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公开(公告)号：US12015006B2
公开(公告)日：2024-06-18
申请号：US17688992
申请日：2022-03-08
Inventor： Shohei Nagai
IPC: H01L23/00
CPC classification number: H01L24/32 , H01L24/29 , H01L24/83 , H01L2224/29111 , H01L2224/32155 , H01L2224/83815 , H01L2924/01029 , H01L2924/0105 , H01L2924/014
Abstract: A semiconductor device includes a substrate, a semiconductor element and a tin-based solder layer. The semiconductor element faces the substrate in a normal direction of the substrate. The normal direction corresponds to a normal line of the substrate. The tin-based solder layer joins the semiconductor element to the substrate. The tin-based solder layer a central portion and a peripheral portion surrounding the central portion. The tin-based solder layer has a tin crystal with a C-axis at each of the central portion and the peripheral portion. The C-axis at the central portion intersects the normal line at an angle larger than 45 degrees with respect to the normal line. The C-axis at the peripheral portion either intersects the normal line at an angle smaller than or equal to 45 degrees with respect to the normal line, or is parallel to the normal line.
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公开(公告)号：US20240170567A1
公开(公告)日：2024-05-23
申请号：US18471581
申请日：2023-09-21
Inventor： RYOTA SUZUKI
CPC classification number: H01L29/7811 , H01L29/0623 , H01L29/1608 , H01L29/7813
Abstract: A semiconductor device includes lower guard rings and upper guard rings. An upper portion of each of the lower guard rings overlaps a lower portion of the corresponding upper guard ring. A lower inner peripheral surface of each of the lower guard rings is offset to one side in a predetermined direction with respect to an upper inner peripheral surface of the corresponding upper guard ring. A lower outer peripheral surface of each of the lower guard rings is offset to the one side in the predetermined direction with respect to an upper outer peripheral surface of the corresponding upper guard ring.
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