公开(公告)号：US20230260871A1

公开(公告)日：2023-08-17

申请号：US18167912

申请日：2023-02-13

申请人： MARVELL ASIA PTE LTD

发明人： Janak G. Patel ,  Richard S. Graf ,  Manish Nayini

IPC分类号： H01L23/427 ,  H01L25/065 ,  H01L23/00

CPC分类号： H01L23/427 ,  H01L25/0652 ,  H01L24/32 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32155 ,  H01L2924/16235 ,  H01L24/16

摘要： An electronic device includes a substrate, and a stack of dies stacked on the substrate. The stack includes (i) multiple dies stacked on one another, the multiple dies include electronic components and interconnections, and (ii) one or more heat pipes (HPs), which are traversing at least a subset of the dies at a right angle relative to the substrate, at least one of the HPs being configured to dissipate heat generated by operation of the electronic components away from at least the subset of the dies.

公开(公告)号：US20180226273A1

公开(公告)日：2018-08-09

申请号：US15885780

申请日：2018-01-31

申请人： SKYWORKS SOLUTIONS, INC.

发明人： Robert Francis DARVEAUX ,  Bruce Joseph FREYMAN ,  Yi LIU

IPC分类号： H01L21/56 ,  H01L23/498 ,  H01L21/48 ,  H01L23/538 ,  H01L25/00 ,  H01L23/00 ,  H01L25/065 ,  H01L21/78 ,  H01L23/29

CPC分类号： H01L21/563 ,  H01L21/0274 ,  H01L21/268 ,  H01L21/481 ,  H01L21/4853 ,  H01L21/4864 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/293 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/544 ,  H01L23/552 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/50 ,  H01L2223/54486 ,  H01L2224/16227 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32155 ,  H01L2224/32225 ,  H01L2224/32227 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83002 ,  H01L2224/83007 ,  H01L2224/831 ,  H01L2224/83855 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/0665 ,  H01L2924/1421 ,  H01L2924/19011 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/00

摘要： Described herein are methods of manufacturing dual-sided packaged electronic modules to control the distribution of an under-fill material between one or more components and a packaging substrate. The disclosed technologies include using a dam on a packaging substrate that is configured to prevent or limit the flow of a capillary under-fill material. This can prevent or limit the capillary under-fill material from flowing onto or contacting other components or elements on the packaging substrate, such as solder balls of a ball-grid array. Accordingly, the disclosed technologies control under-fill for dual-sided ball grid array packages using a dam on a packaging substrate.

公开(公告)号：US20150243591A1

公开(公告)日：2015-08-27

申请号：US14190952

申请日：2014-02-26

申请人： Infineon Technologies AG

发明人： Carsten von Koblinski ,  Ulrike Fastner ,  Andre Brockmeier ,  Peter Zorn

IPC分类号： H01L23/495 ,  H01L21/52 ,  H01L21/78

CPC分类号： H01L21/52 ,  H01L21/4803 ,  H01L21/683 ,  H01L21/78 ,  H01L23/051 ,  H01L23/3677 ,  H01L23/492 ,  H01L23/49861 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/0346 ,  H01L2224/2101 ,  H01L2224/214 ,  H01L2224/215 ,  H01L2224/221 ,  H01L2224/2732 ,  H01L2224/29011 ,  H01L2224/29188 ,  H01L2224/2919 ,  H01L2224/32105 ,  H01L2224/32111 ,  H01L2224/32155 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/82101 ,  H01L2224/82105 ,  H01L2224/82947 ,  H01L2224/83192 ,  H01L2224/83201 ,  H01L2224/9202 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/13055 ,  H01L2924/15156 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2924/0665 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2924/01028 ,  H01L2224/19 ,  H01L2224/83

摘要： A carrier substrate having a plurality of receptacles each for receiving and carrying a semiconductor chip is provided. Semiconductor chips are arranged in the receptacles, and metal is plated in the receptacles to form a metal structure on and in contact with the semiconductor chips. The carrier substrate is cut to form separate semiconductor devices.

摘要翻译： 提供了具有多个用于接收和携带半导体芯片的插座的载体基板。 半导体芯片布置在插座中，金属电镀在插座中以在半导体芯片上形成金属结构并与其接触。 将载体衬底切割以形成分离的半导体器件。

公开(公告)号：US08426963B2

公开(公告)日：2013-04-23

申请号：US13084292

申请日：2011-04-11

申请人： Jian-Hong Zeng ,  Shou-Yu Hong

发明人： Jian-Hong Zeng ,  Shou-Yu Hong

IPC分类号： H01L23/34 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/00 ,  H01L21/44

CPC分类号： H01L23/49524 ,  H01L23/3107 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/73 ,  H01L25/071 ,  H01L25/074 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32155 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2924/1203 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

摘要： A power semiconductor package structure includes a carrier, a first power chip, a second power chip, a first conductive sheet, a second conductive sheet and a third conductive sheet. The first power chip has a first surface and a second surface opposing to the first surface. A first control electrode and a first main power electrode are disposed on the first surface, and a second main power electrode is disposed on the second surface. The second surface is disposed on the carrier, and electrically connected to the carrier through the second main power electrode. The second power chip has a third surface and a fourth surface opposing to the third surface. A third main power electrode is disposed on the third surface, and a fourth main power electrode is disposed on the fourth surface. The fourth surface is disposed on the first power chip. The first conductive sheet is electrically connected to the first main power electrode and the fourth main power electrode. The second conductive sheet is electrically connected to the third main power electrode. The third conductive sheet is electrically connected to the first control electrode. At least a part of the first control electrode is non-covered by the second power chip along a projection direction, which is perpendicular to the carrier.

摘要翻译： 功率半导体封装结构包括载体，第一功率芯片，第二功率芯片，第一导电薄片，第二导电薄片和第三导电薄片。 第一功率芯片具有与第一表面相对的第一表面和第二表面。 第一控制电极和第一主电极设置在第一表面上，第二主电极设置在第二表面上。 第二表面设置在载体上，并通过第二主电极与载体电连接。 第二功率芯片具有与第三表面相对的第三表面和第四表面。 第三主电源电极设置在第三表面上，第四主电源设置在第四表面上。 第四表面设置在第一功率芯片上。 第一导电片电连接到第一主电源电极和第四主电源电极。 第二导电片与第三主电极电连接。 第三导电片与第一控制电极电连接。 第一控制电极的至少一部分沿着垂直于载体的投影方向被第二功率芯片未被覆盖。

公开(公告)号：US20120061833A1

公开(公告)日：2012-03-15

申请号：US12972310

申请日：2010-12-17

申请人： Tae Sung JEONG ,  Doo Hwan LEE ,  Seung Eun LEE

发明人： Tae Sung JEONG ,  Doo Hwan LEE ,  Seung Eun LEE

IPC分类号： H01L23/485 ,  H01L21/60

CPC分类号： H01L24/11 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L2224/2919 ,  H01L2224/32155 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/83001 ,  H01L2224/838 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Disclosed herein are an embedded ball grid array substrate and a manufacturing method thereof. The embedded ball grid array includes: a core layer having a cavity therein; a semiconductor device embedded in the cavity of the core layer; a first circuit layer having a circuit pattern including a wire bonding pad formed thereon; a second circuit layer having a circuit pattern including a solder ball pattern formed thereon; and a wire electrically connecting the semiconductor device to the wire bonding pad.

摘要翻译： 本文公开了嵌入式球栅阵列基板及其制造方法。 嵌入式球栅阵列包括：其中具有空腔的芯层; 嵌入在芯层的空腔中的半导体器件; 第一电路层，具有包括在其上形成的引线接合焊盘的电路图案; 第二电路层，其具有包括形成在其上的焊球图案的电路图案; 以及将半导体器件电连接到引线接合焊盘的线。

公开(公告)号：US20240120452A1

公开(公告)日：2024-04-11

申请号：US18045508

申请日：2022-10-11

申请人： CreeLED, Inc.

发明人： Derek Miller ,  Michael Check ,  Colin Blakely

IPC分类号： H01L33/60 ,  H01L23/00 ,  H01L33/48

CPC分类号： H01L33/60 ,  H01L24/29 ,  H01L33/483 ,  H01L24/32 ,  H01L2224/29083 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29164 ,  H01L2224/32155 ,  H01L2924/0132 ,  H01L2924/12041

摘要： Solid-state lighting devices including light-emitting diodes (LEDs) and, more particularly, reflectors for support structures in LED packages are disclosed. Support structures include arrangements of dielectric reflectors relative to LED chips and electrically conductive traces that are patterned on a submount. Dielectric reflectors include multiple dielectric layer structures that form a distributed Bragg reflector or, in some instances, an aperiodic Bragg reflector. Such dielectric reflectors may be arranged one or more of the electrically conductive traces and on portions of the submount uncovered by the electrically conducive traces to provide increased reflectivity across a variety of wavelengths provided by LED chips, including wavelengths in the ultraviolet spectrum.

公开(公告)号：US11804416B2

公开(公告)日：2023-10-31

申请号：US17444611

申请日：2021-08-06

申请人： UTAC Headquarters Pte. Ltd.

发明人： Saravuth Sirinorakul ,  Preecha Joymak ,  Natawat Kasikornrungroj ,  Wasu Aingkaew ,  Kawin Saiubol ,  Thanawat Jaengkrajarng

IPC分类号： H01L23/31 ,  H01L21/56 ,  H01L23/00

CPC分类号： H01L23/3185 ,  H01L21/565 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/32155 ,  H01L2924/10157

摘要： A semiconductor device has a semiconductor die with a sensor and a cavity formed into a first surface of the semiconductor die to provide access to the sensor. A protective layer is formed on the first surface of the semiconductor die around the cavity. An encapsulant is deposited around the semiconductor die. The protective layer blocks the encapsulant from entering the cavity. With the cavity clear of encapsulant, liquid or gas has unobstructed entry into cavity during operation of the semiconductor die. The clear entry for the cavity provides reliable sensor detection and measurement. The semiconductor die is disposed over a leadframe. The semiconductor die has a sensor. The protective layer can be a film. The protective layer can have a beveled surface. A surface of the leadframe can be exposed from the encapsulant. A second surface of the semiconductor die can be exposed from the encapsulant.

公开(公告)号：US20170338189A1

公开(公告)日：2017-11-23

申请号：US15533245

申请日：2015-10-13

申请人： Mitsubishi Electric Corporation

发明人： Shinnosuke SODA ,  Yohei OMOTO ,  Komei HAYASHI ,  Shinji TSUKAMOTO ,  Yasumichi HATANAKA

IPC分类号： H01L23/00 ,  H01L23/373 ,  H01L23/31 ,  H01L23/367

CPC分类号： H01L23/562 ,  H01L23/13 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3672 ,  H01L23/3735 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/84 ,  H01L25/072 ,  H01L25/115 ,  H01L25/18 ,  H01L2224/291 ,  H01L2224/32155 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/37147 ,  H01L2224/37599 ,  H01L2224/40137 ,  H01L2224/84801 ,  H01L2924/0002 ,  H01L2924/10253 ,  H01L2924/10254 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/1203 ,  H01L2924/13055 ,  H01L2924/14252 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

摘要： An insulated circuit board includes an insulated substrate, a first electrode, and a second electrode. A thin portion is formed in a corner portion, the corner portion being a region occupying, with regard to directions along outer edges from a vertex of at least one of the first and second electrodes in plan view, a portion of a length of the outer edges, and the thin portion has a thickness smaller than that of a region other than the thin portion. The thin portion in at least one of the first and second electrodes has a planar shape surrounded by first and second sides orthogonal to each other as portions of the outer edges from the vertex, and a curved portion away from the vertex of the first and second sides.

公开(公告)号：US20160111410A1

公开(公告)日：2016-04-21

申请号：US14971291

申请日：2015-12-16

申请人： STATS ChipPAC, Ltd.

发明人： Reza A. Pagaila ,  Seng Guan Chow ,  Seung Uk Yoon ,  Byung Tai Do ,  Linda Pei Ee Chua

IPC分类号： H01L25/00 ,  H01L21/56 ,  H01L25/065 ,  H01L21/48 ,  H01L23/31 ,  H01L23/498

CPC分类号： H01L25/50 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/295 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5384 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/82 ,  H01L24/83 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2221/68386 ,  H01L2223/54426 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06131 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/21 ,  H01L2224/2105 ,  H01L2224/215 ,  H01L2224/22 ,  H01L2224/221 ,  H01L2224/24011 ,  H01L2224/2405 ,  H01L2224/24101 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/245 ,  H01L2224/25171 ,  H01L2224/27002 ,  H01L2224/29 ,  H01L2224/2902 ,  H01L2224/29101 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/29298 ,  H01L2224/32155 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48175 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82101 ,  H01L2224/82104 ,  H01L2224/82106 ,  H01L2224/83005 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2224/94 ,  H01L2224/95001 ,  H01L2224/97 ,  H01L2225/06548 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1052 ,  H01L2225/107 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/078 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H05K1/186 ,  H05K3/007 ,  H05K2201/10674 ,  H01L2224/81 ,  H01L2924/01014 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929 ,  H01L2224/03 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device has a first semiconductor die mounted over a carrier. An interposer frame has an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame. The interposer is mounted over the carrier and first die with the conductive pillars disposed around the die. A cavity can be formed in the interposer frame to contain a portion of the first die. An encapsulant is deposited through the opening in the interposer frame over the carrier and first die. Alternatively, the encapsulant is deposited over the carrier and first die and the interposer frame is pressed against the encapsulant. Excess encapsulant exits through the opening in the interposer frame. The carrier is removed. An interconnect structure is formed over the encapsulant and first die. A second semiconductor die can be mounted over the first die or over the interposer frame.

公开(公告)号：US20140170815A1

公开(公告)日：2014-06-19

申请号：US14187202

申请日：2014-02-21

申请人： SAMSUNG ELECTRO-MECHANICS CO., LTD.

发明人： Tae Sung JEONG ,  Doo Hwan LEE ,  Seung Eun LEE

IPC分类号： H01L23/00

CPC分类号： H01L24/11 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L2224/2919 ,  H01L2224/32155 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/83001 ,  H01L2224/838 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Disclosed herein are an embedded ball grid array substrate and a manufacturing method thereof. The embedded ball grid array includes: a core layer having a cavity therein; a semiconductor device embedded in the cavity of the core layer; a first circuit layer having a circuit pattern including a wire bonding pad formed thereon; a second circuit layer having a circuit pattern including a solder ball pattern formed thereon; and a wire electrically connecting the semiconductor device to the wire bonding pad.

摘要翻译： 本文公开了嵌入式球栅阵列基板及其制造方法。 嵌入式球栅阵列包括：其中具有空腔的芯层; 嵌入在芯层的空腔中的半导体器件; 第一电路层，具有包括在其上形成的引线接合焊盘的电路图案; 第二电路层，其具有包括形成在其上的焊球图案的电路图案; 以及将半导体器件电连接到引线接合焊盘的线。