公开(公告)号：US08654830B1

公开(公告)日：2014-02-18

申请号：US12973735

申请日：2010-12-20

Applicant: Andrew Lin ,  Faramarz Bahmani

Inventor： Andrew Lin ,  Faramarz Bahmani

IPC: H03H7/30 ,  H03H7/40 ,  H03K5/159

CPC classification number: H04L25/03057

Abstract: A receiver is optimized by adapting parameters of a linear equalizer component within the receiver. Data decisions and error decisions are generated. These data decision and error decisions are used to derive an error rate of data by measuring the number of margin hits that occur. A balance value is also calculated from the data decisions and the error decisions. The balance value is used to update parameters of the linear equalizer. The updating of the parameter continues until the number of margin hits has been minimized.

Abstract translation: 通过调整接收机内的线性均衡器组件的参数来优化接收机。 生成数据决策和错误决策。 这些数据决定和错误决定用于通过测量发生的边缘匹配数来导出数据的错误率。 还可以从数据决策和错误决策中计算余额值。 平衡值用于更新线性均衡器的参数。 该参数的更新继续，直到边缘命中的数量已被最小化。

公开(公告)号：US08639875B1

公开(公告)日：2014-01-28

申请号：US13226237

申请日：2011-09-06

Applicant: Cristian Estan

Inventor： Cristian Estan

IPC: G06F12/00

CPC classification number: G11C15/04 ,  G06F12/00 ,  G11C15/00 ,  H04L45/7457

Abstract: A CAM-based search engine is disclosed that reduces power consumption during a plurality of different search operations concurrently performed in a plurality of device pipelines by selectively applying one of a number of different power reduction techniques for each pipeline in response to configuration data indicating the type of search operation that is being performed in the pipeline.

Abstract translation: 公开了一种基于CAM的搜索引擎，其通过针对每个流水线选择性地应用多个不同的功率降低技术中的一个来响应于指示类型的配置数据来减少在多个设备管线中并行执行的多个不同的搜索操作期间的功耗 正在执行的搜索操作。

公开(公告)号：US08638582B1

公开(公告)日：2014-01-28

申请号：US13215887

申请日：2011-08-23

Applicant: Dimitri Argyres

Inventor： Dimitri Argyres

IPC: G11C15/00

CPC classification number: G11C15/04 ,  G11C11/56

Abstract: A CAM cell is disclosed that can be selectively configured to store either base-2 data words or base-3 data words. When configured to store base-3 data words, the quaternary CAM cell compares 3 comparand bits representative of a base-3 comparand value with the base-3 data value stored in the CAM cell. Storing base-3 data words in such CAM cells increases the data storage density of associated CAM arrays.

Abstract translation: 公开了可以选择性地配置为存储基2数据字或基3数据字的CAM单元。 当配置为存储基3数据字时，四元CAM单元将表示基3比较值的3个比较位与存储在CAM单元中的基3数据值进行比较。 在这样的CAM单元中存储基3数据字增加了相关CAM阵列的数据存储密度。

公开(公告)号：US20130339558A1

公开(公告)日：2013-12-19

申请号：US13972797

申请日：2013-08-21

Applicant: NetLogic Microsystems, Inc.

Inventor： Julianne J. Zhu ,  David T. Hass

IPC: G06F13/42

CPC classification number: G06F13/4286 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3867 ,  G06F12/0813 ,  H04L49/109

Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. The data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. In one aspect of an embodiment of the invention, the messaging network connects to a high-bandwidth star-topology serial bus such as a PCI express (PCIe) interface capable of supporting multiple high-bandwidth PCIe lanes. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Abstract translation: 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 数据交换机互连通过其相应的数据高速缓存耦合到每个处理器核心，并且消息传递网络通过其各自的消息站耦合到每个处理器核心。 在本发明的实施例的一个方面，消息传递网络连接到能够支持多个高带宽PCIe通道的高带宽星形拓扑串行总线，例如PCI Express（PCIe）接口。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

公开(公告)号：US08589405B1

公开(公告)日：2013-11-19

申请号：US12885176

申请日：2010-09-17

Applicant: Cristian Estan

Inventor： Cristian Estan

IPC: G06F7/00 ,  G06F17/30

CPC classification number: G06F17/30542 ,  G06F17/30985 ,  G06F2221/0711

Abstract: A content search system includes multiple pipelined search engines that implement different portions of a regular expression search operation. For some embodiments, the search pipeline includes a DFA engine, an NFA engine, and a token stitcher that combines partial match results generated by the DFA and NFA engines. The token stitcher can be configured to implement unbounded sub-expressions without utilizing resources of the DFA or NFA engines. A token stitcher may comprise an input line for receiving tokens that indicate a partial match between an input string and a regular expression, a flag bank that stores flags which, when activated, identify one or more of the sub-expressions that match the input string, a program memory that stores programs that each comprises instructions for processing tokens, and an engine configured to identify programs that are associated with a newly received token.

Abstract translation: 内容搜索系统包括实现正则表达式搜索操作的不同部分的多个流水线搜索引擎。 对于一些实施例，搜索流水线包括DFA引擎，NFA引擎和组合由DFA和NFA引擎生成的部分匹配结果的令牌拼接器。 令牌拼接器可以配置为在不使用DFA或NFA引擎的资源的情况下实现无界子表达式。 标记拼接器可以包括用于接收指示输入字符串和正则表达式之间的部分匹配的令牌的输入行，存储标志的标志库，该标志在被激活时标识符合输入字符串的一个或多个子表达 存储程序的程序存储器，每个程序包括用于处理令牌的指令，以及被配置为识别与新接收的令牌相关联的程序的引擎。

公开(公告)号：US08543747B2

公开(公告)日：2013-09-24

申请号：US13253044

申请日：2011-10-04

Applicant: Julianne Jiang Zhu ,  David T. Hass

Inventor： Julianne Jiang Zhu ,  David T. Hass

IPC: G06F13/42 ,  G06F3/00 ,  G06F15/76

CPC classification number: G06F13/4286 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3867 ,  G06F12/0813 ,  H04L49/109

Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. The data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. In one aspect of an embodiment of the invention, the messaging network connects to a high-bandwidth star-topology serial bus such as a PCI express (PCIe) interface capable of supporting multiple high-bandwidth PCIe lanes. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Abstract translation: 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 数据交换机互连通过其相应的数据高速缓存耦合到每个处理器核心，并且消息传递网络通过其各自的消息站耦合到每个处理器核心。 在本发明的实施例的一个方面，消息传递网络连接到能够支持多个高带宽PCIe通道的高带宽星形拓扑串行总线，例如PCI Express（PCIe）接口。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

公开(公告)号：US08494377B1

公开(公告)日：2013-07-23

申请号：US12828125

申请日：2010-06-30

Applicant: Halil Cirit

Inventor： Halil Cirit

IPC: H04B10/00 ,  H04B10/58

CPC classification number: H04B10/58 ,  H04B10/2507

Abstract: Transmitter waveform dispersion penalty (“TWDP”) is decreased in a transmitter. A binary data signal is received for transmission over a channel that exhibits TWDP. The data signal is shifted less than a full clock cycle to generate at least one post cursor signal. The post cursor signal is subtracted from the data signal to generate a transmitter output data signal for transmission over the channel. In addition to decreasing TWDP, data dependent jitter is also reduced for data transmission across a channel that exhibits a multi-pole transmission characteristic. A main data signal and at least one cursor signal, which is shifted at least a portion of a clock period from the main data signal, is generated. The cursor signal is filtered to filter out effects based on the second pole of the multi-pole transmission characteristic. The main data signal is subtracted from the filtered cursor signal to generate the transmitter output data signal. Circuits and methods for transmitting serial data streams over a channel compliant with KR and SPI specifications are also disclosed.

Abstract translation: 发射机中的发射机波形色散损失（“TWDP”）减小。 接收二进制数据信号以通过展现TWDP的信道进行传输。 数据信号被移动小于一整个时钟周期以产生至少一个后光标信号。 从数据信号中减去后光标信号，以产生用于在信道上传输的发射机输出数据信号。 除了降低TWDP之外，数据相关的抖动也减少了跨越显示多极传输特性的通道的数据传输。 产生主数据信号和至少一个光标信号，其被从主数据信号的至少一部分时钟周期移位。 对光标信号进行滤波以滤除基于多极传输特性的第二极点的效果。 从经滤波的光标信号中减去主数据信号，以产生发射机输出数据信号。 还公开了通过符合KR和SPI规范的信道发送串行数据流的电路和方法。

公开(公告)号：US20130159612A1

公开(公告)日：2013-06-20

申请号：US13762927

申请日：2013-02-08

Applicant: NetLogic Microsystems, Inc.

Inventor： Marc LOINAZ

IPC: G06F12/02 ,  G06F1/08

CPC classification number: G06F12/0246 ,  G06F1/08

Abstract: Embodiments of the invention relate to programmable data register circuits and programmable clock generation circuits For example, some embodiments include a buffer circuit for receiving input data and sending output data signals along a series of signal lines with a signal strength, and a signal modulator configured to determine the signal strength based on a control input. Some embodiments include a clock generation circuit for receiving clock reference and sending output clock signals along a series of signal lines with a signal character, and a signal modulator configured to determine the signal character based on a control input.

Abstract translation: 本发明的实施例涉及可编程数据寄存器电路和可编程时钟生成电路。例如，一些实施例包括用于接收输入数据并沿着具有信号强度的一系列信号线发送输出数据信号的缓冲电路，以及配置为 根据控制输入确定信号强度。 一些实施例包括用于接收时钟参考并且沿着一系列具有信号字符的信号线发送输出时钟信号的时钟产生电路，以及被配置为基于控制输入来确定信号字符的信号调制器。

公开(公告)号：US08423814B2

公开(公告)日：2013-04-16

申请号：US12728101

申请日：2010-03-19

Applicant: Marc Loinaz

Inventor： Marc Loinaz

IPC: G06F1/00 ,  G06F5/06 ,  G06F13/00

CPC classification number: G06F12/0246 ,  G06F1/08

Abstract: Embodiments of the invention relate to programmable data register circuits and programmable clock generation circuits For example, some embodiments include a buffer circuit for receiving input data and sending output data signals along a series of signal lines with a signal strength, and a signal modulator configured to determine the signal strength based on a control input. Some embodiments include a clock generation circuit for receiving clock reference and sending output clock signals along a series of signal lines with a signal character, and a signal modulator configured to determine the signal character based on a control input.

Abstract translation: 本发明的实施例涉及可编程数据寄存器电路和可编程时钟生成电路。例如，一些实施例包括用于接收输入数据并沿着具有信号强度的一系列信号线发送输出数据信号的缓冲电路，以及配置为 根据控制输入确定信号强度。 一些实施例包括用于接收时钟参考并且沿着一系列具有信号字符的信号线发送输出时钟信号的时钟产生电路，以及被配置为基于控制输入来确定信号字符的信号调制器。

公开(公告)号：US08416673B1

公开(公告)日：2013-04-09

申请号：US12406023

申请日：2009-03-17

Applicant: Karen Hovakimyan ,  Gaurav Malhotra

Inventor： Karen Hovakimyan ,  Gaurav Malhotra

IPC: H04J1/12 ,  H04J3/10

CPC classification number: H04B3/32

Abstract: A method and system are described for canceling far end cross-talk in communication systems. A first transmitter transmits the first effective data source signals across the first channel. A second transmitter transmits the second effective data source signals across the second channel. In one embodiment, a receiver unit receives first and second effective data source signals across a first channel and a second channel, respectively, and also one or more cross-talk signals. A far end cross talk (FEXT) canceller located in the receiver unit receives second estimated effective data source signals based on the second effective data source signals. The receiver unit cancels the one or more cross-talk signals using the second estimated effective data source signals.

Abstract translation: 描述了一种方法和系统，用于消除通信系统中的远端串扰。 第一发射机跨越第一信道发送第一有效数据源信号。 第二发射机跨越第二信道发送第二有效数据源信号。 在一个实施例中，接收机单元分别跨第一通道和第二通道接收第一和第二有效数据源信号，以及一个或多个串扰信号。 位于接收机单元中的远端串扰（FEXT）消除器基于第二有效数据源信号接收第二估计有效数据源信号。 接收机单元使用第二估计有效数据源信号来取消一个或多个串扰信号。