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公开(公告)号：US20210104457A1
公开(公告)日：2021-04-08
申请号：US17064119
申请日：2020-10-06
Inventor： David AUCHERE , Claire LAPORTE , Deborah COGONI , Laurent SCHWARTZ
Abstract: An electronic device includes a carrier substrate with an electronic IC chip mounted on top of the carrier substrate. An encapsulation block on top of the front face of the carrier substrate embeds the IC chip. The encapsulation block has a through-void for positioning and confinement that extends through the encapsulation block to the top of the carrier substrate. At least one electronic component is positioned within the through-void and mounted to the top of the carrier substrate. Solder bumps or pads are located within the through-void to electrically connect the at least one electronic component to the carrier substrate.
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公开(公告)号：US10944359B2
公开(公告)日：2021-03-09
申请号：US16207751
申请日：2018-12-03
Inventor： Benoit Marchand , Francois Druilhe
Abstract: A quartz crystal resonator is coupled to an electronic circuit. A capacitive or resistive element is provided for adjusting a frequency of the quartz crystal resonator on activation or deactivation of a function of a circuit. Control is made according to a model of an expected variation of a temperature of the quartz crystal resonator.
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公开(公告)号：US10944358B2
公开(公告)日：2021-03-09
申请号：US16207696
申请日：2018-12-03
Inventor： Benoit Marchand , Francois Druilhe
Abstract: A quartz crystal resonator is connected to an array of switchable capacitors or resistors. The switched actuation of elements of the array is controlled by bits of a control word. At least one of the bits of the control word is controlled by pulse width modulation to effectuate a tuning of the oscillation frequency of the quartz crystal resonator.
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公开(公告)号：US10924100B2
公开(公告)日：2021-02-16
申请号：US16849020
申请日：2020-04-15
Applicant: STMicroelectronics S.r.l. , STMicroelectronics (Alps) SAS
Inventor： Giovanni Luca Torrisi , Domenico Porto , Christophe Roussel
Abstract: An H-bridge circuit includes a supply voltage node, a first pair of transistors and a second pair of transistors. First transistors in each pair have the current paths therethrough included in current flow lines between the supply node and, respectively, a first output node and a second output node. Second transistors in each pair have the current paths therethrough coupled to a third output node and a fourth output node, respectively. The first and third output nodes are mutually isolated from each other and the second and fourth output nodes are mutually isolated from each other. The H-bridge circuit is operable in a selected one of a first, second and third mode.
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公开(公告)号：US10886844B2
公开(公告)日：2021-01-05
申请号：US16719656
申请日：2019-12-18
Applicant: STMicroelectronics (Alps) SAS
Inventor： Alexandre Pons
Abstract: A controller for compensating a voltage drop on a cable includes an output stage coupled to a channel configuration pin of the source device, a processor coupled to a power supply pin of a source device, and an error amplifier that includes a positive input coupled to a reference voltage, a negative input coupled to the channel configuration pin, a first output coupled to the output stage, and a second output coupled to the processor. The error amplifier is configured to supply a first signal to the output stage indicating a voltage difference between the reference voltage and a voltage at the channel configuration pin. The output stage is configured to supply an output current to the processor using the voltage drop and a stored current determined using the first signal. The processor is configured to generate a compensated supply voltage on the power supply pin using the output current.
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Patent Agency Ranking
公开(公告)号：US20200335466A1
公开(公告)日：2020-10-22
申请号：US16847934
申请日：2020-04-14
Inventor： Laurent SCHWARTZ , David KAIRE , Jerome LOPEZ
IPC: H01L23/00
Abstract: A bumping matrix includes many bumps, wherein each bump is rotationally asymmetric in a plane of the bumping matrix. The bumps are orientated in a centripetal arrangement. Bumps in a first portion of the bumping matrix have a first pitch in a first axis and bumps in a second portion of the bumping matrix have a second pitch in the first axis. The second pitch is different from the first pitch. Bumps have an oblong shape with a longer diameter and a shorter diameter. The centripetal arrangement orients the longer diameter of the bumps is a direction radially extending from a center of the bumping matrix.
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公开(公告)号：US10811349B2
公开(公告)日：2020-10-20
申请号：US16110121
申请日：2018-08-23
Inventor： David Auchere , Laurent Schwarz , Deborah Cogoni , Eric Saugier
IPC: H01L23/498 , H01L23/538 , H01L23/00 , H05K1/18 , H01L23/31 , H01L23/13 , H01L21/56 , H01L21/78
Abstract: An electronic device includes a support wafer, an electronic chip and an encapsulating block for the electronic chip above the support wafer. The support wafer is provided with a first network of electrical connections and a second network of electrical connections formed solely by tracks. First electrical connection elements are interposed between first front electrical contacts of the electronic chip and rear electrical contacts of the first network. Second electrical connection elements are interposed between second front electrical contacts of the electronic chip and internal electrical contact zones of the tracks of the second network. The first network includes front external electrical contacts and the tracks exhibiting external electrical contact zones.
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公开(公告)号：US10803911B2
公开(公告)日：2020-10-13
申请号：US15884229
申请日：2018-01-30
Applicant: STMICROELECTRONICS (ALPS) SAS
Inventor： Patrik Arno
Abstract: A current sense amplifier includes: first and second intermediate nodes coupled to first and second nodes of a sense resistor by a chopper, and to respective branches of a current mirror; a differential amplifier having inputs coupled to the first and second intermediate nodes and adapted to generate first and second voltage signals; and first and second transistors adapted to be controlled by the first and second voltage signals respectively and each having one of its main current conducting nodes coupled to a respective one of the first and second intermediate nodes.
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公开(公告)号：US20200257323A1
公开(公告)日：2020-08-13
申请号：US16787679
申请日：2020-02-11
Inventor： Jean CAMIOLO , Alexandre PONS
IPC: G05F1/575 , H03K3/0233 , H03F3/45 , G05F3/18 , G01R19/165 , G06F1/26
Abstract: A first terminal receives a first DC voltage. A switch selectively couples the first terminal to a second terminal providing an output. A control circuit selectively actuates the switch in response to a comparison of the first DC voltage to a second DC voltage. A low-dropout (LDO) linear voltage regulator, connected between the first and third terminals, operates to provide the second DC voltage from the first DC voltage.
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公开(公告)号：US10580807B2
公开(公告)日：2020-03-03
申请号：US15792556
申请日：2017-10-24
Applicant: STMicroelectronics, Inc. , STMICROELECTRONICS (ALPS) SAS
Inventor： Frederic Morestin , Alexandre Balmefrezol , Rui Xiao
IPC: H04N5/369 , H01L27/146 , H04N9/04 , H04N5/355 , G01S1/00
Abstract: The present disclosure is directed to an image sensor including a pixel array of both range pixels and color pixels. Each range pixel (or range pixel area) may be associated with multiple adjacent color pixels, with each side of the range pixel immediately adjacent to at least two color pixels. The association between the range pixels and the color pixels may be dynamically configurable. The readings of a range pixel(s) and the associated color pixels may be integrated together in the generation of a 3D image.
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