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公开(公告)号：US10910438B2
公开(公告)日：2021-02-02
申请号：US16400943
申请日：2019-05-01
Applicant: Micron Technology, Inc.
Inventor： Fabio Pellizzer , Lorenzo Fratin , Hongmei Wang
IPC: H01L21/66 , H01L23/528 , H01L23/532 , H01L27/24 , H01L45/00
Abstract: Methods, systems, and devices for memory arrays having graded memory stack resistances are described. An apparatus may include a first subset of memory stacks having a first resistance based on a physical and/or electrical distance of the first subset of memory stacks from at least one of a first driver component or a second driver component. The apparatus may include a second subset of memory stacks having a second resistance that is less than the first resistance based on a physical and/or electrical distance of the second subset of memory from at least one of the first driver component or the second driver component.
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公开(公告)号：US20210005665A1
公开(公告)日：2021-01-07
申请号：US16460875
申请日：2019-07-02
Applicant: Micron Technology, Inc.
Inventor： Paolo Fantini , Fabio Pellizzer , Lorenzo Fratin
Abstract: Methods, systems, and devices for split pillar architectures for memory devices are described. A memory device may include a substrate arranged with conductive contacts in a pattern and openings through alternative layers of conductive and insulative material that may decrease the spacing between the openings while maintaining a dielectric thickness to sustain the voltage to be applied to the array. After etching material, an insulative material may be deposited in a trench. Portions of the insulative material may be removed to form openings, into which cell material is deposited. Conductive pillars may extend perpendicular to the planes of the conductive material and the substrate, and couple to conductive contacts. The conductive pillars may be divided to form first and second pillars.
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公开(公告)号：US20200381046A1
公开(公告)日：2020-12-03
申请号：US16998240
申请日：2020-08-20
Applicant: Micron Technology, Inc.
Inventor： Andrea Redaelli , Innocenzo Tortorelli , Agostino Pirovano , Fabio Pellizzer
Abstract: Methods, systems, and devices for multi-deck memory arrays are described. A multi-deck memory device may include a memory array with a cell having a self-selecting memory element and another array with a cell having a memory storage element and a selector device. The device may be programmed to store multiple combinations of logic states using cells of one or more decks. Both the first deck and second deck may be coupled to at least two access lines and may have one access line that is a common access line, coupling the two decks. Additionally, both decks may overlie control circuitry, which facilitates read and write operations. The control circuitry may be configured to write a first state or a second state to one or both of the memory decks via the access lines.
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公开(公告)号：US20200372966A1
公开(公告)日：2020-11-26
申请号：US16990114
申请日：2020-08-11
Applicant: Micron Technology, Inc.
Inventor： Innocenzo Tortorelli , Agostino Pirovano , Andrea Redaelli , Fabio Pellizzer , Hongmei Wang
Abstract: Methods, systems, and devices for drift mitigation with embedded refresh are described. A memory cell may be written to and read from using write and read voltages, respectively, that are of different polarities. For example, a memory cell may be written to by applying a first write voltage and may be subsequently read from by applying a first read voltage of a first polarity. At least one additional (e.g., a second) read voltage—a setback voltage—of a second polarity may be utilized to return the memory cell to its original state. Thus the setback voltage may mitigate a shift in the voltage distribution of the cell caused by the first read voltage.
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公开(公告)号：US20200321522A1
公开(公告)日：2020-10-08
申请号：US16856631
申请日：2020-04-23
Applicant: Micron Technology, Inc.
Inventor： Agostino Pirovano , Kolya Yastrebenetsky , Anna Maria Conti , Fabio Pellizzer
Abstract: Methods, systems, and devices for memory cells with asymmetrical electrode interfaces are described. A memory cell with asymmetrical electrode interfaces may mitigate shorts in adjacent word lines, which may be leveraged for accurately reading a stored value of the memory cell. The memory device may include a self-selecting memory component with a top surface area in contact with a top electrode and a bottom surface area in contact with a bottom electrode, where the top surface area in contact with the top electrode is a different size than the bottom surface area in contact with the bottom electrode.
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Patent Agency Ranking
公开(公告)号：US20200321520A1
公开(公告)日：2020-10-08
申请号：US16904385
申请日：2020-06-17
Applicant: Micron Technology, Inc.
Inventor： Lorenzo Fratin , Fabio Pellizzer
Abstract: A self-selecting memory cell may be composed of a memory material that changes threshold voltages based on the polarity of the voltage applied across it. Such a memory cell may be formed at the intersection of a conductive pillar and electrode plane in a memory array. A dielectric material may be formed between the memory material of the memory cell and the corresponding electrode plane. The dielectric material may form a barrier that prevents harmful interactions between the memory material and the material that makes up the electrode plane. In some cases, the dielectric material may also be positioned between the memory material and the conductive pillar to form a second dielectric barrier. The second dielectric barrier may increase the symmetry of the memory array or prevent harmful interactions between the memory material and an electrode cylinder or between the memory material and the conductive pillar.
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公开(公告)号：US20200266343A1
公开(公告)日：2020-08-20
申请号：US16866302
申请日：2020-05-04
Applicant: Micron Technology, Inc.
Inventor： Fabio Pellizzer , Innocenzo Tortorelli , Andrea Ghetti
Abstract: The disclosed technology generally relates to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. Line stacks are formed, including a storage material line disposed over lower a conductive line. Upper conductive lines are formed over and crossing the line stacks, exposing portions of the line stacks between adjacent upper conductive lines. After forming the upper conductive lines, storage elements are formed at intersections between the lower conductive lines and the upper conductive lines by removing storage materials from exposed portions of the line stacks, such that each storage element is laterally surrounded by spaces. A continuous sealing material laterally surrounds each of the storage elements.
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公开(公告)号：US20200243136A1
公开(公告)日：2020-07-30
申请号：US16257521
申请日：2019-01-25
Applicant: Micron Technology, Inc.
Inventor： Agostino Pirovano , Fabio Pellizzer
Abstract: Methods, systems, and devices for polarity-written cell architectures for a memory device are described. In an example, the described architectures may include memory cells that each include or are otherwise associated with a material configured to store one of a set of logic states based at least in part on a polarity of a write voltage applied to the material. Each of the memory cells may also include a cell selection component configured to selectively couple the material with an access line. In some examples, the material may include a chalcogenide, and the material may be configured to store each of the set of logic states in an amorphous state of the chalcogenide. In various examples, different logic states may be associated with different compositional distributions of the material of a respective memory cell, different threshold characteristics of the material of a respective memory cell, or other characteristics.
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公开(公告)号：US10707271B2
公开(公告)日：2020-07-07
申请号：US16216100
申请日：2018-12-11
Applicant: Micron Technology, Inc.
Inventor： Fabio Pellizzer , Andrea Redaelli , Agostino Pirovano , Innocenzo Tortorelli
Abstract: The present disclosure includes memory cells having resistors, and methods of forming the same. An example method includes forming a first conductive line, forming a second conductive line, and forming a memory element between the first conductive line and the second conductive line. Forming the memory element can include forming one or more memory materials, and forming a resistor in series with the one or more memory materials. The resistor can be configured to reduce a capacitive discharge through the memory element during a state transition of the memory element.
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公开(公告)号：US10680037B2
公开(公告)日：2020-06-09
申请号：US15688027
申请日：2017-08-28
Applicant: Micron Technology, Inc.
Inventor： Paolo Fantini , Cristina Casellato , Fabio Pellizzer
IPC: H01L21/764 , H01L21/762 , H01L21/768 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/1157 , H01L27/24 , H01L45/00
Abstract: A cross-point memory array includes a plurality of variable resistance memory cell pillars. Adjacent memory cell pillars are separated by a partially filled gap that includes a buried void. In addition, adjacent memory cell pillars include storage material elements that are at least partially interposed by the buried void.
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