公开(公告)号：US08358524B1

公开(公告)日：2013-01-22

申请号：US12215875

申请日：2008-06-27

Applicant: Martin Fabry

Inventor： Martin Fabry

IPC: G11C15/00

CPC classification number: G11C15/04 ,  G11C15/00

Abstract: A content addressable memory (CAM) device can include a number of bit line. One or more of the bit lines can be connected to storage circuits of CAM cells in a corresponding column. Each CAM cell can include compare circuits that compare a stored value one or more compare data values. An isolation circuit can have a controllable impedance path connected between the bit line and a precharge voltage node and can be controlled by application of a potential at a control node. A control circuit can be coupled to the control node and can switch the isolation circuit from a high impedance state to a low impedance state in response to, and no later than the start of, an access operation.

Abstract translation: 内容可寻址存储器（CAM）设备可以包括多个位线。 一个或多个位线可以连接到相应列中的CAM单元的存储电路。 每个CAM单元可以包括比较电路，其比较存储的值一个或多个比较数据值。 隔离电路可以具有连接在位线和预充电电压节点之间的可控阻抗路径，并且可以通过在控制节点处施加电位来控制。 控制电路可以耦合到控制节点，并且可以响应于并且不迟于进入操作的开始，将隔离电路从高阻抗状态切换到低阻抗状态。

公开(公告)号：US20130009619A1

公开(公告)日：2013-01-10

申请号：US13618652

申请日：2012-09-14

Applicant: Sandeep Khanna ,  Maheshwaran Srinivasan ,  De Cai Li ,  Chetan Deshpande

Inventor： Sandeep Khanna ,  Maheshwaran Srinivasan ,  De Cai Li ,  Chetan Deshpande

IPC: G05F1/10

CPC classification number: H02M3/1584 ,  H02M2003/1586 ,  Y10T307/582

Abstract: An integrated circuit device for delivering power to a load includes a controller circuit, a cascade circuit, and a power delivery circuit. The controller circuit generates a plurality of control signals. The cascade circuit receives the control signals from the controller circuit and sequentially outputs the control signals onto a cascade bus. The power delivery circuit receives the control signals from the controller circuit and delivers an amount of current to the load, in response to one of the control signals.

Abstract translation: 用于向负载递送电力的集成电路装置包括控制器电路，级联电路和电力输送电路。 控制器电路产生多个控制信号。 级联电路从控制器电路接收控制信号，并将控制信号依次输出到级联总线上。 功率传递电路响应于控制信号之一，接收来自控制器电路的控制信号并将一定量的电流传送到负载。

公开(公告)号：US08340171B2

公开(公告)日：2012-12-25

申请号：US12421521

申请日：2009-04-09

Applicant: Karen Hovakimyan ,  Igor Djokovic

Inventor： Karen Hovakimyan ,  Igor Djokovic

IPC: H04L27/01 ,  H04B1/10

CPC classification number: H04J11/0033 ,  H04L25/03343 ,  H04L25/497 ,  H04L25/4975

Abstract: An improved Tomlinson Harashima Precoding (THP) communication system through special configuration of its feedback coefficients is disclosed. Improvement, in terms of THP system robustness against analog-to-digital (ADC) sampling phase variation, is achieved either by deriving feedback coefficients of the Decision Feedback Equalizer at worst ADC sampling phase or by inserting a Zero Edge Filter (ZEF) at the receiver. The ZEF modifies the communication system such that the feedback filter coefficients derived in the Decision Feedback Equalizer (DFE) mode and later used in the THP mode is capable to compensate the zero at Nyquist Frequency due to a non-optimum sampling, phase of the ADC. The THP communication system, modified and improved with the insertion of ZEF, is operable to switch from an adaptive Decision Feedback Equalizer (DFE) mode to a THP mode having an adaptive Linear Equalizer (LE) at the receiver.

Abstract translation: 公开了通过其反馈系数的特殊配置改进的Tomlinson Harashima Precoding（THP）通信系统。 在THP系统对模数（ADC）采样相位变化的鲁棒性方面的改进可以通过在最差的ADC采样阶段推导出判决反馈均衡器的反馈系数，或者通过在零点边沿滤波器（ZEF）中插入零边沿滤波器 接收器。 ZEF修改通信系统，使得在判决反馈均衡器（DFE）模式下导出的以后在THP模式中使用的反馈滤波器系数能够由于ADC的非最佳采样相位而补偿奈奎斯特频率处的零点 。 通过插入ZEF进行修改和改进的THP通信系统可操作以在接收机处从自适应判决反馈均衡器（DFE）模式切换到具有自适应线性均衡器（LE）的THP模式。

公开(公告)号：US20120288094A1

公开(公告)日：2012-11-15

申请号：US13555783

申请日：2012-07-23

Applicant: Roy G. Batruni

Inventor： Roy G. Batruni

IPC: H04L9/00

CPC classification number: H04L9/0668 ,  H04K1/00 ,  H04L27/00

Abstract: A system and method are disclosed for securely transmitting and receiving a signal. A nonlinear keying modulator is used in the transmitter to encrypt the signal using a nonlinear keying modulation technique. A nonlinear keying demodulator is used in the receiver to decrypt the signal.

Abstract translation: 公开了用于安全地发送和接收信号的系统和方法。 发射机使用非线性密钥调制器，使用非线性密钥调制技术对信号进行加密。 在接收机中使用非线性键控解调器对信号进行解密。

公开(公告)号：US08285974B2

公开(公告)日：2012-10-09

申请号：US11830727

申请日：2007-07-30

Applicant: Gaurav Singh ,  Srivatsan Srinivasan ,  Lintsung Wong

Inventor： Gaurav Singh ,  Srivatsan Srinivasan ,  Lintsung Wong

IPC: G06F9/30

CPC classification number: G06F9/3814 ,  G06F9/3838

Abstract: An apparatus for queue allocation. An embodiment of the apparatus includes a dispatch order data structure, a bit vector, and a queue controller. The dispatch order data structure corresponds to a queue. The dispatch order data structure stores a plurality of dispatch indicators associated with a plurality of pairs of entries of the queue to indicate a write order of the entries in the queue. The bit vector stores a plurality of mask values corresponding to the dispatch indicators of the dispatch order data structure. The queue controller interfaces with the queue and the dispatch order data structure. The queue controller excludes at least some of the entries from a queue operation based on the mask values of the bit vector.

Abstract translation: 一种用于队列分配的装置。 该装置的实施例包括调度顺序数据结构，位向量和队列控制器。 调度订单数据结构对应于一个队列。 调度订单数据结构存储与队列的多对条目相关联的多个调度指示符，以指示队列中条目的写入顺序。 位向量存储对应于调度顺序数据结构的调度指示符的多个掩码值。 队列控制器与队列和调度订单数据结构接口。 队列控制器基于位向量的掩码值从队列操作中排除至少一些条目。

公开(公告)号：US08274265B1

公开(公告)日：2012-09-25

申请号：US12028774

申请日：2008-02-08

Applicant: Sandeep Khanna ,  Maheshwaran Srinivasan ,  De Cai Li ,  Chetan Deshpande

Inventor： Sandeep Khanna ,  Maheshwaran Srinivasan ,  De Cai Li ,  Chetan Deshpande

IPC: G05F1/59 ,  G05F1/618

CPC classification number: H02M3/1584 ,  H02M2003/1586 ,  Y10T307/582

Abstract: An integrated circuit device for delivering power to a load includes a controller circuit, a cascade circuit, and a power delivery circuit. The controller circuit generates a plurality of control signals. The cascade circuit receives the control signals from the controller circuit and sequentially outputs the control signals onto a cascade bus. The power delivery circuit receives the control signals from the controller circuit and delivers an amount of current to the load, in response to one of the control signals.

Abstract translation: 用于向负载递送电力的集成电路装置包括控制器电路，级联电路和电力输送电路。 控制器电路产生多个控制信号。 级联电路从控制器电路接收控制信号，并将控制信号依次输出到级联总线上。 功率传递电路响应于控制信号之一，接收来自控制器电路的控制信号并将一定量的电流传送到负载。

公开(公告)号：US08229119B2

公开(公告)日：2012-07-24

申请号：US12008709

申请日：2008-01-10

Applicant: Roy G. Batruni

Inventor： Roy G. Batruni

IPC: H04L9/00

Abstract: A system and method are disclosed for securely transmitting and receiving a signal. A nonlinear keying modulator is used in the transmitter to encrypt the signal using a nonlinear keying modulation technique. A nonlinear keying demodulator is used in the receiver to decrypt the signal.

公开(公告)号：US08176298B2

公开(公告)日：2012-05-08

申请号：US10930938

申请日：2004-08-31

Applicant: David T. Hass

Inventor： David T. Hass

IPC: G06F9/00

CPC classification number: H04L49/00 ,  G06F12/0813 ,  H04L49/90

Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Abstract translation: 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

公开(公告)号：US20120089762A1

公开(公告)日：2012-04-12

申请号：US13253044

申请日：2011-10-04

Applicant: Julianne Jiang Zhu ,  David T. Hass

Inventor： Julianne Jiang Zhu ,  David T. Hass

IPC: G06F13/14

CPC classification number: G06F13/4286 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3867 ,  G06F12/0813 ,  H04L49/109

Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. The data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. In one aspect of an embodiment of the invention, the messaging network connects to a high-bandwidth star-topology serial bus such as a PCI express (PCIe) interface capable of supporting multiple high-bandwidth PCIe lanes. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Abstract translation: 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 数据交换机互连通过其相应的数据高速缓存耦合到每个处理器核心，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。 在本发明的实施例的一个方面，消息传递网络连接到能够支持多个高带宽PCIe通道的高带宽星形拓扑串行总线，例如PCI Express（PCIe）接口。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

公开(公告)号：US08155236B1

公开(公告)日：2012-04-10

申请号：US10176495

申请日：2002-06-21

Applicant: Stefanos Sidiropoulos ,  Haw-Jyh Liaw

Inventor： Stefanos Sidiropoulos ,  Haw-Jyh Liaw

IPC: H04L25/34

CPC classification number: H04L7/0008 ,  H04L7/0337 ,  H04L25/068

Abstract: A data receiver circuit includes a transmission line to generate the appropriate timing for clock and data recovery. The transmission line receives a reference signal, and propagates the reference signal through at least two segments of predetermined lengths. The transmission line is configured with a first tab to extract, from the first predetermined length, a first delayed signal, and a second tab to extract, from the second predetermined length, a second delayed signal. A sampling circuit generates samples, at a first time period, from an input signal and the first delayed signal. The sampling circuit also generates samples, at a second time period, from the input signal and the second delayed signal. A capacitance control device to adjust the capacitance of the transmission line is disclosed. The data receiver circuit and the transmission line may be both fabricated on an integrated circuit, or the transmission line may be implemented external to the integrated circuit chip, such as on a package housing of the integrated circuit chip or on a printed circuit board for which the integrated circuit chip is mounted.

Abstract translation: 数据接收器电路包括用于产生用于时钟和数据恢复的适当定时的传输线。 传输线接收参考信号，并通过预定长度的至少两个段传播参考信号。 传输线配置有第一标签以从第一预定长度提取第一延迟信号，以及第二标签，以从第二预定长度提取第二延迟信号。 采样电路在第一时间段从输入信号和第一延迟信号产生采样。 采样电路还在第二时间段从输入信号和第二延迟信号产生采样。 公开了一种用于调节传输线的电容的电容控制装置。 数据接收器电路和传输线可以都是在集成电路上制造的，或者传输线可以在集成电路芯片的外部实现，例如在集成电路芯片的封装外壳上或印刷电路板上， 安装集成电路芯片。