公开(公告)号：US08331138B1

公开(公告)日：2012-12-11

申请号：US13103038

申请日：2011-05-06

申请人： David Richard Trossen ,  Malcolm John Wing

发明人： David Richard Trossen ,  Malcolm John Wing

IPC分类号： G11C11/50

CPC分类号： G11C13/025 ,  B82Y10/00 ,  G11C23/00 ,  Y10S977/708 ,  Y10S977/732 ,  Y10S977/943

摘要： A configuration bit array including a hybrid electromechanical and semiconductor memory cell, and circuitry for addressing and controlling read, write, and erase accesses of the memory.

摘要翻译： 包括混合机电和半导体存储器单元的配置位阵列以及用于寻址和控制存储器的读，写和擦除存取的电路。

公开(公告)号：US08222917B2

公开(公告)日：2012-07-17

申请号：US11591734

申请日：2006-11-02

申请人： Antonietta Oliva ,  Louis Charles Kordus ,  Vei-Han Chan

发明人： Antonietta Oliva ,  Louis Charles Kordus ,  Vei-Han Chan

IPC分类号： H03K17/16 ,  H03K19/003

CPC分类号： H04L25/0278 ,  H03H7/38

摘要： Impedance matching and trimming apparatuses and methods using programmable resistance devices. According to one exemplary embodiment, the impedance matching circuit includes a programmable resistance element, a comparator, a resistor divider having a common node coupled to a first input of the comparator, and an impedance element control circuit coupled between an output of the comparator and the programmable resistance element. The programmable resistance element includes one or more programmable resistance devices (PRDs). Programmed resistances of the programmable resistance element combine with the resistance of an external reference resistor to provide an impedance matched termination. A change in the resistance of the termination impedance causes a change in the output of the comparator. The impedance element control circuit responds to changes in the output of the comparator by providing one or more program control output signals, which control the resistance values of one or more of the PRDs, thereby maintaining an impedance matched termination.

摘要翻译： 使用可编程电阻器件的阻抗匹配和修整设备和方法。 根据一个示例性实施例，阻抗匹配电路包括可编程电阻元件，比较器，具有耦合到比较器的第一输入的公共节点的电阻器分压器，以及耦合在比较器的输出和 可编程电阻元件。 可编程电阻元件包括一个或多个可编程电阻器件（PRD）。 可编程电阻元件的编程电阻与外部参考电阻的电阻相结合，提供阻抗匹配的端接。 端接阻抗的电阻变化导致比较器输出的变化。 阻抗元件控制电路通过提供控制一个或多个PRD的电阻值的一个或多个程序控制输出信号来响应比较器输出的变化，从而保持阻抗匹配的终止。

公开(公告)号：US20110317720A1

公开(公告)日：2011-12-29

申请号：US13226195

申请日：2011-09-06

申请人： Malcolm J. Wing ,  Jay B. Patel ,  Jeffrey M. Schroeder

发明人： Malcolm J. Wing ,  Jay B. Patel ,  Jeffrey M. Schroeder

IPC分类号： H04J99/00

CPC分类号： H04L43/18 ,  H04L69/12 ,  H04L69/22 ,  H04L69/324

摘要： A system for parsing frames including a first cell extraction circuit (CEC) configured to identify a first cell from a first frame, a first parser engine operatively connected to the first CEC, where the first parser engine is configured to generate a result based on the first cell, and a first forwarding circuit operatively connected to the first parser engine and configured to forward the result, where the first CEC, the first parser engine, and the first forwarding circuit are associated with a first frame parser unit.

摘要翻译： 一种用于解析帧的系统，包括被配置为从第一帧识别第一小区的第一小区提取电路（CEC），可操作地连接到第一CEC的第一解析器引擎，其中第一解析器引擎被配置为基于 第一单元和第一转发电路，其可操作地连接到第一解析器引擎并且被配置为转发结果，其中第一CEC，第一解析器引擎和第一转发电路与第一帧解析器单元相关联。

公开(公告)号：US07885103B2

公开(公告)日：2011-02-08

申请号：US11285535

申请日：2005-11-22

申请人： David Richard Trossen ,  Malcolm John Wing

发明人： David Richard Trossen ,  Malcolm John Wing

IPC分类号： G11C11/50

CPC分类号： G11C13/025 ,  B82Y10/00 ,  G11C23/00 ,  Y10S977/708 ,  Y10S977/732 ,  Y10S977/943

摘要： A configuration bit array including a hybrid electromechanical and semiconductor memory cell, and circuitry for addressing and controlling read, write, and erase accesses of the memory.

公开(公告)号：US07814136B1

公开(公告)日：2010-10-12

申请号：US11344694

申请日：2006-02-01

申请人： Hare K. Verma ,  Ravi Sunkavalli ,  Manoj Gunwani

发明人： Hare K. Verma ,  Ravi Sunkavalli ,  Manoj Gunwani

IPC分类号： G06F7/38

CPC分类号： G06F7/483 ,  G06F7/5443 ,  G06F7/57 ,  H03K19/17736

摘要： A programmable system is disclosed having multiple configurable floating point units (“FPU”) that are coupled to multiple programmable logic and routing blocks and multiple memories. Each floating point unit has static configuration blocks and dynamic configuration blocks, where the dynamic configuration blocks can be reconfigured to perform a different floating point unit function. A floating point unit includes a pre-normalization for shifting an exponent calculation as well as shifting and aligning a mantissa, and a post-normalization for normalizing and rounding a received input. The post-normalization receives an input Z and realigns the input, normalizes the input and rounds the input Z.

摘要翻译： 公开了一种可编程系统，其具有耦合到多个可编程逻辑和路由块和多个存储器的多个可配置浮点单元（“FPU”）。 每个浮点单元具有静态配置块和动态配置块，其中动态配置块可以被重新配置以执行不同的浮点单元功能。 浮点单元包括用于移位指数计算以及移位和对准尾数的预归一化，以及用于归一化和舍入所接收的输入的后归一化。 后归一化接收输入Z并重新对准输入，对输入进行归一化并舍入输入Z。

公开(公告)号：US07728623B2

公开(公告)日：2010-06-01

申请号：US11539757

申请日：2006-10-09

申请人： Hare K. Verma ,  Ravi Sunkavalli ,  Sudip Nag ,  Conrad Kong ,  Bo Hu ,  Chandra Mulpuri ,  Ashok Vittal

发明人： Hare K. Verma ,  Ravi Sunkavalli ,  Sudip Nag ,  Conrad Kong ,  Bo Hu ,  Chandra Mulpuri ,  Ashok Vittal

IPC分类号： H03K19/177

CPC分类号： H03K19/17736

摘要： A programmable logic structure is disclosed employing input logic routing cell (ILRC) multiplexers and output logic routing cell (OLRC) multiplexers for making local connections between dedicated logic cells. In a simple programmable logic structure, a dedicated logic cell (DLC) is implemented in a programmable logic structure comprising multiple ILRC multiplexers for port A and multiple OLRC multiplexers for port B. In a multi-level programmable logic structure, multiple columns of dedicated logic cells is designed with columns of dedicated local cells adjacent to each other where each DLC column is used to implement a particular logic function. In a first embodiment, local connections can be made between dedicated logic cells, e.g. an OLRC in a first DLC at level L making local point-to-point connections to an ILRC in a second DLC at level L+1. In a second embodiment, local connections can be made from any other dedicated logic cells, whether positioned horizontally or vertically relative to a relative point or multiplexer, and from any offset from a current logic and routing cell (LRC). In a third embodiment, local connections can be made by stitching a first OLRC to a second OLRC (for connecting to an ILRC), which allows lines from other columns or levels of DLC to reach an ILRC for a fast local interconnect.

摘要翻译： 公开了一种使用输入逻辑路由单元（ILRC）多路复用器和输出逻辑路由单元（OLRC）多路复用器进行专用逻辑单元之间的本地连接的可编程逻辑结构。 在简单的可编程逻辑结构中，专用逻辑单元（DLC）以包括用于端口A的多个ILRC多路复用器和用于端口B的多个OLRC多路复用器的可编程逻辑结构实现。在多级可编程逻辑结构中，多列专用逻辑 单元被设计成具有彼此相邻的专用本地单元的列，其中每个DLC列用于实现特定的逻辑功能。 在第一实施例中，可以在专用逻辑单元之间进行本地连接。 在L级的第一个DLC中的OLRC在L + 1级的第二个DLC中与ILRC进行本地点对点连接。 在第二实施例中，可以从任何其他专用逻辑单元进行本地连接，无论相对于相对点或多路复用器是水平还是垂直的，以及来自当前逻辑和路由单元（LRC）的任何偏移。 在第三实施例中，可以通过将第一OLRC拼接到第二OLRC（用于连接到ILRC）来实现本地连接，这允许来自其他列或DLC级的线路到达用于快速本地互连的ILRC。

公开(公告)号：US07725863B2

公开(公告)日：2010-05-25

申请号：US11712308

申请日：2007-02-27

申请人： Ernst Mayer

发明人： Ernst Mayer

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： The present invention relates to methods for the global and detail routing of integrated circuits with hierarchical interconnect routing architecture. The methods includes the steps of: mapping routing resources of said integrated circuit to the nodes and edges of a graph theoretic tree, mapping each target to a target node; mapping each driver to a driver node; and routing each driver and its targets as a function of the minimum spanning tree spanning each driver node and its target nodes by traversing from the target nodes of a driver backwards toward its driver node in said tree. The methods of this invention are straightforward to implement, of polynomial time complexity, and can optimize routing resource usage.

摘要翻译： 本发明涉及具有分层互连路由架构的集成电路的全局和详细路由的方法。 所述方法包括以下步骤：将所述集成电路的路由资源映射到图理论树的节点和边缘，将每个目标映射到目标节点; 将每个驱动程序映射到驱动程序节点; 并且通过从驱动器的目标节点向后朝向所述树中的驱动器节点遍历每个驱动器及其目标作为跨越每个驱动器节点及其目标节点的最小生成树的函数。 本发明的方法直接实现多项式时间复杂度，并可以优化路由资源的使用。

公开(公告)号：US07719449B2

公开(公告)日：2010-05-18

申请号：US12196036

申请日：2008-08-21

申请人： Nadeem Fahmi ,  Jason Alexander Jones

发明人： Nadeem Fahmi ,  Jason Alexander Jones

IPC分类号： H03M9/00

CPC分类号： H03M9/00

摘要： A system including a serializer/deserializer (SERDES) block including a first SERDES lane, a second SERDES lane, a third SERDES lane, and a fourth SERDES lane; a physical coding sublayer (PCS) block including a layout select tag, a first PCS lane connected to the fourth SERDES lane, a second PCS lane connected to the third SERDES lane, a third PCS lane connected to the second SERDES lane, and a fourth PCS lane connected to the first SERDES lane; and a media access control (MAC) layer block including a first plurality of pins connected to the first PCS lane, a second plurality of pins connected to the second PCS lane, a third plurality of pins connected to the third PCS lane, and a fourth plurality of pins connected to the fourth PCS lane, wherein the PCS block is configured to map the first SERDES lane to the first plurality of pins, the second SERDES lane to the second plurality of pins, the third SERDES lane to the third plurality of pins, and the fourth SERDES lane to the fourth plurality of pins based on a value of the layout select tag.

摘要翻译： 一种包括串行器/解串器（SERDES）块的系统，包括第一SERDES通道，第二SERDES通道，第三SERDES通道和第四SERDES通道; 包括布局选择标签的物理编码子层（PCS）块，连接到第四SERDES通道的第一PCS通道，连接到第三SERDES通道的第二PCS通道，连接到第二SERDES通道的第三PCS通道，以及第四 PCS车道连接到第一个SERDES车道; 以及媒体访问控制（MAC）层块，包括连接到第一PCS通道的第一多个引脚，连接到第二PCS通道的第二多个引脚，连接到第三PCS通道的第三多个引脚，以及第四个 多个引脚连接到第四PCS通道，其中PCS块被配置为将第一SERDES通道映射到第一多个引脚，第二SERDES通道到第二个多个引脚，第三个SERDES通道与第三个多个引脚 以及基于布局选择标签的值的与第四多个引脚的第四SERDES通道。

公开(公告)号：US07009421B2

公开(公告)日：2006-03-07

申请号：US10951309

申请日：2004-09-27

申请人： Daniel J. Pugh ,  Andrew W. Fox ,  Dale Wong

发明人： Daniel J. Pugh ,  Andrew W. Fox ,  Dale Wong

IPC分类号： H03K19/173 ,  G06F17/50

CPC分类号： G06F17/5054

摘要： A Field Programmable Gate Array (FPGA) core cell with one or more Look-Up Tables (LUTs) and a selectable logic gate is presented as a space-efficient alternative to the conventional LUT-based FPGA core cell. An algorithm based upon the familiar FlowMap algorithm for LUT-based FPGA core cells implements the mapping of a Boolean logic network into the disclosed FPGA core cell.

公开(公告)号：US09071246B2

公开(公告)日：2015-06-30

申请号：US11855740

申请日：2007-09-14

申请人： Suresh Subramaniam ,  Mukunda Krishnappa ,  Pohrong R. Chu ,  Jason Golbus ,  Dana L. How

发明人： Suresh Subramaniam ,  Mukunda Krishnappa ,  Pohrong R. Chu ,  Jason Golbus ,  Dana L. How

IPC分类号： G11C7/00 ,  H03K19/177 ,  G06F13/16

CPC分类号： G06F17/5054 ,  G06F13/1668 ,  G06F17/505 ,  G06F17/5077 ,  G11C7/00 ,  H03K19/177 ,  Y02D10/14

摘要： A system including a configurable memory controller, a memory interface, and a configurable high speed communications fabric comprising a plurality of interconnect stations arranged in an array and operable to implement a plurality of pipelined buses, where the configurable memory controller is operably coupled to the configurable high speed communications fabric using a first interconnect station of the plurality of interconnect stations, where the memory interface is operably coupled to the configurable high speed communications fabric using a second interconnect station of the plurality of interconnect stations, where the plurality of interconnect stations are configured to satisfy a timing requirement of the memory interface, and where the configurable memory controller, the memory interface, and the configurable high speed communications fabric are associated with a configurable integrated circuit.

摘要翻译： 一种包括可配置存储器控制器，存储器接口和可配置高速通信结构的系统，其包括布置在阵列中并可操作以实现多个流水线总线的多个互连站，其中可配置存储器控制器可操作地耦合到可配置 高速通信结构，其使用所述多个互连站中的第一互连站，其中所述存储器接口使用所述多个互连站中的第二互连站可操作地耦合到所述可配置高速通信结构，其中所述多个互连站被配置 以满足存储器接口的定时要求，并且其中可配置存储器控制器，存储器接口和可配置高速通信结构与可配置集成电路相关联。