公开(公告)号：US20120278517A1

公开(公告)日：2012-11-01

申请号：US13513526

申请日：2010-12-06

Applicant: Peter Korger

Inventor： Peter Korger

IPC: G06F5/14

CPC classification number: H04L49/9047 ,  H04L49/90

Abstract: An assembly where a number of receivers receiving packets for storing in queues in a storage and a means for de-queuing data from the storage. A controller determines addresses for the storage, the address being determined on the basis of at least a fill level of the queue(s), where information relating to de-queues addresses is only read-out when the fill-level(s) exceed a limit so as to not spend bandwidth on this information before it is required.

Abstract translation: 其中多个接收器接收用于存储在存储器中的队列中的分组并且用于从存储器排队数据的装置的组件。 控制器确定存储的地址，该地址基于至少一个或多个队列的填充级别确定，其中与排队地址有关的信息仅在填充级别超过时被读出 限制，以便在需要之前不要在此信息上花费带宽。

公开(公告)号：US07711006B2

公开(公告)日：2010-05-04

申请号：US10564731

申请日：2004-08-13

Applicant: William M. Dries ,  Kathryn E. Rickard

Inventor： William M. Dries ,  Kathryn E. Rickard

IPC: H04J3/24

CPC classification number: H04L47/10 ,  H04J3/247 ,  H04L47/22 ,  H04L49/90 ,  H04L49/9094

Abstract: A data merge unit is provided for providing an interleaved data stream, the data stream including data frames received on two or more input channels, wherein data frames from each of the two or more input channels are arranged in time-slots of the interleaved data stream. The data merge unit comprises an input unit to receive data frames from two or more input channels, a frame merge buffer arranged to receive data frames from the two or more input channels via the input unit and store said data frames; and, an output generator to generate the interleaved data stream, the output generator being configured to select complete data frames from the frame merge buffer and arrange said complete data frames in the interleaved data stream.

Abstract translation: 提供数据合并单元，用于提供交错数据流，所述数据流包括在两个或多个输入通道上接收的数据帧，其中来自两个或更多个输入通道中的每一个的数据帧被布置在交错数据流的时隙中 。 该数据合并单元包括：一个输入单元，用于从两个或多个输入通道接收数据帧;帧合并缓冲器，被布置成经由输入单元从两个或多个输入通道接收数据帧，并存储所述数据帧; 以及输出生成器，用于生成交错数据流，所述输出生成器被配置为从所述帧合并缓冲器中选择完整数据帧，并且将所述完整数据帧排列在所述交错数据流中。

公开(公告)号：US10467196B2

公开(公告)日：2019-11-05

申请号：US15281208

申请日：2016-09-30

Applicant: Napatech A/S

Inventor： Hans-Martin Brændmose Jensen ,  Michael Milde Lilja

IPC: G06F7/00 ,  G06F16/17

Abstract: The invention relates to a method for storing files in a data storage. The method comprises steps of providing the data storage with a plurality of data files all having the same predetermined size and a step of subsequently storing new data in the data storage by including the new data in a new data file having the predetermined size and overwriting an existing data file with the new data file.

公开(公告)号：US10211939B2

公开(公告)日：2019-02-19

申请号：US14900001

申请日：2014-06-27

Applicant: Napatech A/S

Inventor： Nicolai Asbjørn Smitt

IPC: H04J3/06 ,  H04L7/00 ,  G06F5/06

Abstract: Forwarding points in time of a clock over a clock boundary is performed by launching the points in time into a buffer, such as a FIFO, in the first clock domain. The oldest point in time is fed into a FIFO or delay line in the other clock domain, which FIFO or delay line comprises a plurality of received points in time, which are shifted through the FIFO or delay line over time. An estimate of a point in time in the second clock domain is derived from a plurality of the points in time in the delay line/FIFO, such as from a mean value thereof. This point in time may be compensated for a known delay in order for this determined point in time to be identical to or close to an actual point in time of the first clock in the first clock domain.

公开(公告)号：US20160277322A1

公开(公告)日：2016-09-22

申请号：US15034252

申请日：2014-11-11

Applicant: NAPATECH A/S

Inventor： Jens Christophersen

IPC: H04L12/935 ,  H04L12/741 ,  H04L12/861

CPC classification number: H04L49/3036 ,  H04L45/74 ,  H04L49/00 ,  H04L49/9078

Abstract: A system and a method for analysing a plurality of data packets where the data packets are analysed to determine which of a number of subsequent process(es) is/are to further analyse the data packets. Information identifying the subsequent process(es) is added to a FIFO. An unknown data packet type is not immediately recognizable, whereby a storage location is reserved in the FIFO, and the data packet is fed to a separate characterizing process deriving the information relating to the relevant process(es), which information is subsequently fed to the relevant storage location in the FIFO, so that the order of data packets represented in the FIFO is the order of receipt of the data packets. From the FIFO, information is fed to a work list or storage of the relevant subsequent processes to process the pertaining data packets. This processing may also be in the chronological order of receipt of the data packets.

Abstract translation: 一种用于分析数据分组被分析的多个数据分组的系统和方法，以确定多个后续处理中的哪一个是/进一步分析数据分组。 识别后续过程的信息被添加到FIFO。 未知数据分组类型不能被立即识别，由此在FIFO中保留存储位置，并且将数据分组馈送到导出与相关进程相关的信息的单独特征化过程，该信息随后被馈送到 FIFO中的相关存储位置，使得在FIFO中表示的数据分组的顺序是接收数据分组的顺序。 从FIFO中，将信息馈送到相关后续处理的工作列表或存储器以处理相关数据分组。 该处理也可以是接收数据分组的时间顺序。

公开(公告)号：US09407581B2

公开(公告)日：2016-08-02

申请号：US13513520

申请日：2010-12-06

Applicant: Peter Korger ,  Peter Ekner

Inventor： Peter Korger ,  Peter Ekner

IPC: H04L12/56 ,  H04L1/00 ,  H04L7/00 ,  G06F1/12 ,  H04L12/861 ,  H04L12/879

CPC classification number: H04L49/9047 ,  H04L49/901

Abstract: An apparatus and a method where a plurality of physically separate data receiving/analyzing elements receive data packets and time stamp these. A controlling unit determines a storing address for each data packet based on at least the time stamp, where the controlling unit does not perform the determination of the address until a predetermined time delay has elapsed after the time of receipt.

Abstract translation: 一种其中多个物理分离的数据接收/分析元件接收数据分组并对其进行时间戳记的装置和方法。 控制单元至少基于时间戳确定每个数据分组的存储地址，其中控制单元不执行地址的确定，直到在接收时间过去了预定的时间延迟。

公开(公告)号：US08934341B2

公开(公告)日：2015-01-13

申请号：US13513522

申请日：2010-12-06

Applicant: Peter Korger

Inventor： Peter Korger

IPC: H04L1/00 ,  H04L12/863 ,  H04L12/803 ,  H04L12/861 ,  H04L12/875

CPC classification number: H04L47/6255 ,  H04L47/125 ,  H04L47/568 ,  H04L49/90 ,  H04L49/9047

Abstract: An assembly and a method where a number of receiving units receive and store data in a number of queues de-queued by a plurality of processors/processes. If a selected queue for one processor has a fill level exceeding a limit, the packet is forwarded to a queue of another processor which is instructed to not de-queue that queue until the queue with the exceeded fill level has been emptied. Thus, load balancing between processes/processors may be obtained while maintaining an ordering between packets.

Abstract translation: 一种组装和方法，其中多个接收单元在由多个处理器/处理排队的多个队列中接收和存储数据。 如果一个处理器的选定队列具有超过限制的填充级别，则将数据包转发到另一个处理器的队列，该队列被指示为不排队该队列，直到具有超出的填充级别的队列已被清空。 因此，可以在保持分组之间的排序的同时获得进程/处理器之间的负载平衡。

公开(公告)号：US20140211816A1

公开(公告)日：2014-07-31

申请号：US14238753

申请日：2012-08-30

Applicant: Peter Ekner

Inventor： Peter Ekner

IPC: H04J3/06

CPC classification number: H04J3/0697 ,  H04L7/0012 ,  H04L7/0331 ,  H04L7/04

Abstract: A de-serializer, such as forming part of a SERDES, in which a point in time of receipt, on the serial data path, of receipt of a particular part of a data packet, such as an SOF, is determined from when that part is output on the parallel data path from knowledge of the clock controlling the parallel data path as well as which of the parallel lanes the part is output on.

Abstract translation: 在串行数据路径上接收到数据分组的特定部分（例如SOF）的接收的时间段中的诸如形成SERDES的一部分的解串器化器从该部分 从控制并行数据路径的时钟知识以及部分输出的并行通道中的哪一条信号输出到并行数据路径上。

公开(公告)号：US20120281703A1

公开(公告)日：2012-11-08

申请号：US13513329

申请日：2010-12-06

Applicant: Alex Omø Agerholm ,  Jens Christophersen

Inventor： Alex Omø Agerholm ,  Jens Christophersen

IPC: H04L12/56

CPC classification number: H04L43/18 ,  H04L43/026 ,  H04L47/10 ,  H04L47/34 ,  H04L49/552

Abstract: A system and a method of operating the system, the system having a plurality of data receiving elements each receiving data packets from a data connection and from another receiving element and forwarding the two data packets to another receiving element in a predetermined order. If, at a point in time, only one data packet is received, a period of time is allowed to elapse, and if a second data packet is received, the two packets are output in the order. If not, the received data packet is output.

Abstract translation: 一种操作系统的系统和方法，所述系统具有多个数据接收元件，每个数据接收元件从数据连接和另一个接收元件接收数据包，并以预定顺序将两个数据包转发到另一个接收元件。 如果在某个时间点仅接收到一个数据分组，则允许经过一段时间，如果接收到第二数据分组，则按顺序输出两个分组。 如果不是，则输出接收到的数据分组。