System and a method of analysing a plurality of data packets

    公开(公告)号:US10033665B2

    公开(公告)日:2018-07-24

    申请号:US15034252

    申请日:2014-11-11

    Applicant: Napatech A/S

    Abstract: A system and a method for analyzing a plurality of data packets where the data packets are analyzed to determine which of a number of subsequent process(es) is/are to further analyze the data packets. Information identifying the subsequent process(es) is added to a FIFO. An unknown data packet type is not immediately recognizable, whereby a storage location is reserved in the FIFO, and the data packet is fed to a separate characterizing process deriving the information relating to the relevant process(es), which information is subsequently fed to the relevant storage location in the FIFO, so that the order of data packets represented in the FIFO is the order of receipt of the data packets. From the FIFO, information is fed to a work list or storage of the relevant subsequent processes to process the pertaining data packets. This processing may also be in the chronological order of receipt of the data packets.

    System and a method of deriving information

    公开(公告)号:US09811110B2

    公开(公告)日:2017-11-07

    申请号:US14924876

    申请日:2015-10-28

    Applicant: Napatech A/S

    CPC classification number: G06F1/04 G06F3/05 H04J3/0697

    Abstract: A system and a method of sampling an event signal using multiple clocking signals each provided in a separate candidate clock domain each of which also receives points in time from a master clock. From each candidate clock domain, clocked by the individual clocking signals, pairs of a received point in time and event signal value are fed to a master clock domain. In the master clock domain, the values of the event signal may be determined over time as a function of master clock time. This may be used for synchronizing operation in the master clock domain of e.g. packet time stamping with an overall time defined by the event signal. Using multiple clocking signals for the sampling, a much more precise sampling of the event signal is facilitated.

    System and a method of deriving information
    6.
    发明申请
    System and a method of deriving information 有权
    系统和一种导出信息的方法

    公开(公告)号:US20160116935A1

    公开(公告)日:2016-04-28

    申请号:US14924876

    申请日:2015-10-28

    Applicant: Napatech A/S

    CPC classification number: G06F1/04 G06F3/05 H04J3/0697

    Abstract: A system and a method of sampling an event signal using multiple clocking signals each provided in a separate candidate clock domain each of which also receives points in time from a master clock. From each candidate clock domain, clocked by the individual clocking signals, pairs of a received point in time and event signal value are fed to a master clock domain. In the master clock domain, the values of the event signal may be determined over time as a function of master clock time. This may be used for synchronizing operation in the master clock domain of e.g. packet time stamping with an overall time defined by the event signal. Using multiple clocking signals for the sampling, a much more precise sampling of the event signal is facilitated.

    Abstract translation: 一种使用多个时钟信号对事件信号采样的系统和方法,每个时钟信号分别在单独的候选时钟域中提供,每个时钟信号也从主时钟接收时间点。 从每个候选时钟域,由各个时钟信号计时,接收的时间点和事件信号值的对被馈送到主时钟域。 在主时钟域中,事件信号的值可以随时间而被确定为主时钟时间的函数。 这可以用于例如主时钟域中的同步操作。 分组时间戳由事件信号定义的总时间。 使用多个时钟信号进行采样,便于对事件信号进行更精确的采样。

    System and a method for handling data
    8.
    发明申请

    公开(公告)号:US20180167322A1

    公开(公告)日:2018-06-14

    申请号:US15839216

    申请日:2017-12-12

    Applicant: Napatech A/S

    Abstract: A system and a method for receiving data packets at the inputs of two data handlers. Each data handler compares address data in the individual data packet with a first and a second list of addresses and forward packets to each other, so that data packets with one of the first addresses are fed to one data handler and packets with one of the second addresses are fed to the other data handler. The data handlers output the data packets received so that one data handler outputs all packets with addresses of the first addresses and the other data handler outputs all packets with addresses of the second addresses.

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