公开(公告)号：US20130318419A1

公开(公告)日：2013-11-28

申请号：US13829553

申请日：2013-03-14

Applicant: Changkyu Seol ,  Junjin Kong ,  Hong Rak Son

Inventor： Changkyu Seol ,  Junjin Kong ,  Hong Rak Son

IPC: G06F11/14 ,  G06F12/02 ,  H03M13/05

CPC classification number: G06F12/0246 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/26 ,  G11C2211/5644 ,  H03M13/05 ,  H03M13/251

Abstract: A flash memory system which includes a flash memory and a memory controller. The flash memory is configured to perform a read operation using a plurality of read levels. The memory controller is configured to recover original data using a counter value provided from the flash memory. The flash memory converts read result values obtained using the plurality of read levels into the counter value to provide the counter value to the memory controller.

Abstract translation: 一种包括闪存和存储器控制器的闪存系统。 闪速存储器被配置为使用多个读取电平执行读取操作。 存储器控制器被配置为使用从闪存提供的计数器值来恢复原始数据。 闪速存储器将使用多个读取电平获得的读取结果值转换为计数器值，以将计数器值提供给存储器控制器。

公开(公告)号：US20120268988A1

公开(公告)日：2012-10-25

申请号：US13413118

申请日：2012-03-06

Applicant: CHANGKYU SEOL ,  EUNCHEOL KIM ,  JUNJIN KONG ,  HONG RAK SON

Inventor： CHANGKYU SEOL ,  EUNCHEOL KIM ,  JUNJIN KONG ,  HONG RAK SON

IPC: G11C16/10 ,  G11C16/04

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/0408 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  G11C16/3427 ,  G11C2211/5641 ,  H01L27/11578

Abstract: A nonvolatile memory device includes a memory cell array having multiple memory blocks. Each memory block includes memory cells arranged at intersections of multiple word lines and multiple bit lines. At least one word line of the multiple word lines is included in an upper word line group and at least one other word line of the multiple word lines is included in a lower word line group. The number of data bits stored in memory cells connected to the at least one word line included in the upper word line group is different from the number of data bits stored in memory cells connected to the at least one other word line included in the lower word line group.

Abstract translation: 非易失性存储器件包括具有多个存储块的存储单元阵列。 每个存储块包括布置在多个字线和多个位线的交点处的存储器单元。 多个字线的至少一个字线被包括在上部字线组中，并且多个字线的至少一个其它字线被包括在下部字线组中。 连接到包括在上部字线组中的至少一个字线的存储器单元中存储的数据位的数量不同于存储在连接到包含在下一个字中的至少一个其它字线的存储器单元中的数据位的数量 线组。