公开(公告)号：US08976849B2

公开(公告)日：2015-03-10

申请号：US12523934

申请日：2007-01-22

Applicant: Patrick Pratt ,  Hari Thirumoorthy ,  Conor O'Keeffe

Inventor： Patrick Pratt ,  Hari Thirumoorthy ,  Conor O'Keeffe

IPC: H04L27/14 ,  H03D3/00 ,  H04L27/00

CPC classification number: H03D3/009 ,  H04L27/0014 ,  H04L2027/0016

Abstract: A calibration signal generator for use in a balancing circuit calibration device in a radio receiver, the calibration signal generator comprising: a means of amplifying a clocking signal from a clocking signal generator to provide a first calibration signal; a means of generating a second calibration signal from the clocking signal, the first and second calibration signals being transmissible to a one or more mixing circuits in the balancing circuit calibration device; and a means synchronizing the operation of other circuit elements in the balancing circuit calibration device with the clocking signal; characterized in that the clocking signal generator is present in the radio receiver and used therein for other functions.

Abstract translation: 一种用于无线电接收机中的平衡电路校准装置的校准信号发生器，所述校准信号发生器包括：放大来自时钟信号发生器的时钟信号以提供第一校准信号的装置; 从所述时钟信号产生第二校准信号的装置，所述第一和第二校准信号可传输到所述平衡电路校准装置中的一个或多个混合电路; 以及将平衡电路校准装置中的其他电路元件的操作与时钟信号同步的装置; 其特征在于，时钟信号发生器存在于无线电接收机中并在其中用于其它功能。

公开(公告)号：US08942655B2

公开(公告)日：2015-01-27

申请号：US12600687

申请日：2007-05-31

Applicant: Norman Beamish ,  Conor O'Keeffe ,  Patrick Pratt

Inventor： Norman Beamish ,  Conor O'Keeffe ,  Patrick Pratt

IPC: H04B17/00 ,  H04B1/10 ,  H04B1/26 ,  H04B1/16 ,  H03D3/00 ,  H04B1/30 ,  H04L27/00

CPC classification number: H03D3/009 ,  H04B1/30 ,  H04L27/0014

Abstract: An integrated circuit comprising processing logic for operably coupling to radio frequency (RF) receiver circuitry arranged to receive a wireless network signal. The receiver circuitry generates in-phase and quadrature digital baseband representations of the wireless network signal. The processing logic determines quadrature (I/Q) imbalance of the RF receiver circuitry based on the in-phase and quadrature digital baseband representations of the wireless network signal.

Abstract translation: 一种集成电路，包括用于可操作地耦合到布置成接收无线网络信号的射频（RF）接收机电路的处理逻辑。 接收器电路产生无线网络信号的同相和正交数字基带表示。 处理逻辑基于无线网络信号的同相和正交数字基带表示来确定RF接收器电路的正交（I / Q）不平衡。

公开(公告)号：US20140153590A1

公开(公告)日：2014-06-05

申请号：US14171921

申请日：2014-02-04

Applicant: Paul Kelleher ,  Michael O'Brien ,  Conor O'Keeffe

Inventor： Paul Kelleher ,  Michael O'Brien ,  Conor O'Keeffe

IPC: H04W56/00

CPC classification number: H04W56/0045 ,  H04B1/40 ,  H04B15/02 ,  H04B2215/067

Abstract: A semiconductor device comprising interface logic for transmitting data bursts across an interface. The interface logic is arranged to transmit bursts of data across the interface such that the start of a burst of data is substantially aligned with a symbol interval (SI) boundary. The interface logic is further arranged to apply an offset to the SI boundary at the start of the burst of data.

Abstract translation: 一种半导体器件，包括用于通过接口传输数据脉冲串的接口逻辑。 接口逻辑被布置成通过接口传输数据脉冲串，使得数据突发的开始基本上与符号间隔（SI）边界对齐。 接口逻辑还被布置为在数据突发的开始处向SI边界应用偏移。

公开(公告)号：US08707079B2

公开(公告)日：2014-04-22

申请号：US13061967

申请日：2008-09-04

Applicant: Michael O'brien ,  Paul Kelleher ,  Conor O'keeffe

Inventor： Michael O'brien ,  Paul Kelleher ,  Conor O'keeffe

IPC: G06F1/00 ,  G06F13/14 ,  H04B15/00 ,  H04B1/04

CPC classification number: H04B15/02

Abstract: A semiconductor device comprising an interface logic module for transmitting data frames across an interface, and controller logic module arranged to control a rate at which the interface logic transmits data across the interface. Upon receipt of data frames to transmit across the interface, the controller logic module is arranged to determine a sequence of data rates with which to transmit sequential data frames across the interface, and to configure the transmission of the data frames across the interface according to the determined data rate sequence. The selection of these data rates will be dependent on specific critical RF frequencies where EMI impacts have to be minimized.

Abstract translation: 一种半导体器件，包括用于跨接口传输数据帧的接口逻辑模块，以及控制器逻辑模块，被配置为控制接口逻辑在接口上传输数据的速率。 在接收到通过接口传输的数据帧之后，控制器逻辑模块被配置为确定跨接口传输顺序数据帧的数据速率序列，并且根据接口配置跨接口的数据帧的传输 确定的数据速率序列。 这些数据速率的选择将取决于必须最小化EMI影响的特定关键RF频率。

公开(公告)号：US08532225B2

公开(公告)日：2013-09-10

申请号：US12919536

申请日：2008-03-19

Applicant: Conor O'Keeffe ,  Norman Beamish ,  Richard Verellen

Inventor： Conor O'Keeffe ,  Norman Beamish ,  Richard Verellen

IPC: H04L25/06

CPC classification number: H04L25/062

Abstract: Receiver circuitry for processing a received Very Low Intermediate Frequency signal wherein the receiver circuitry comprises a main processing path. The main processing path comprises mixing circuitry arranged to mix a received VLIF signal with a frequency down conversion signal to produce a main path signal. The receiver circuitry further comprises a direct current cancellation path comprising mixing circuitry arranged to mix a DC element of the received VLIF signal with the frequency down conversion signal to produce a DC cancellation signal. The receiver circuitry still further comprises signal summing circuitry arranged to add the DC cancellation signal in anti-phase with the main path signal.

Abstract translation: 用于处理接收到的非常低中频信号的接收器电路，其中接收器电路包括主处理路径。 主处理路径包括混合电路，其被布置为将接收的VLIF信号与降频转换信号混合以产生主路径信号。 接收器电路还包括直流消除路径，其包括混合电路，其被布置为将所接收的VLIF信号的DC元件与降频转换信号混合以产生DC消除信号。 接收器电路还包括信号求和电路，其被布置为将DC抵消信号与主路径信号反相地相加。

公开(公告)号：US08391415B2

公开(公告)日：2013-03-05

申请号：US12522047

申请日：2007-01-09

Applicant: Paul Kelleher ,  Diarmuid McSwiney ,  Conor O'Keeffe

Inventor： Paul Kelleher ,  Diarmuid McSwiney ,  Conor O'Keeffe

IPC: H03K9/00

CPC classification number: H04L7/042 ,  H04B1/005 ,  H04B1/70753 ,  H04L7/0337

Abstract: An electronic device comprises a number of sub-systems coupled via an interface. One of the number of sub-systems comprises logic for receiving a frame of input data having a plurality of phases on respective data paths. The electronic device further comprises logic for performing cross correlation on the received input data with a pre-determined bit pattern, operably coupled to selection logic, for selecting a single phase from the plurality of phases sent to the interface to sample the received input data in a middle region of a data bit period in response to the cross correlation.

Abstract translation: 电子设备包括通过接口耦合的多个子系统。 子系统中的一个包括用于接收在相应数据路径上具有多个相位的输入数据帧的逻辑。 电子设备还包括用于以可选择地耦合到选择逻辑的预定比特模式对所接收的输入数据执行互相关的逻辑，用于从发送到接口的多个相位中选择单相以对接收到的输入数据进行采样 响应于互相关的数据位周期的中间区域。

公开(公告)号：US20120196591A1

公开(公告)日：2012-08-02

申请号：US13382616

申请日：2010-06-15

Applicant: Conor O'Keeffe ,  Joe Moore

Inventor： Conor O'Keeffe ,  Joe Moore

IPC: H04W24/00

CPC classification number: H01Q3/2605 ,  H01Q1/246

Abstract: A wireless network element is operably couplable to an antenna array for communicating with at least one remote wireless communication unit. The antenna array comprises a plurality of radiating elements where at least one first radiating element of the plurality of radiating elements is arranged to create a radiation pattern in a sector of a communication cell. The wireless network element comprises a receiver arranged to receive and process at least one signal from the at least one remote wireless communication unit via the at least one first radiating element. The wireless network element also comprises a beam scanning module for stepping/sweeping the radiation pattern through the sector of the communication cell, such that at least one signal from the at least one remote wireless communication unit is processed to identify signal parameters representative of incoming signal power and angle of arrival of the received at least one signal.

Abstract translation: 无线网络元件可操作地耦合到天线阵列，用于与至少一个远程无线通信单元进行通信。 天线阵列包括多个辐射元件，其中多个辐射元件中的至少一个第一辐射元件被布置成在通信单元的扇区中产生辐射图。 所述无线网元包括接收器，所述接收器被布置成经由所述至少一个第一辐射元件接收并处理来自所述至少一个远程无线通信单元的至少一个信号。 无线网络元件还包括用于通过通信小区的扇区对辐射模式进行步进/扫描的波束扫描模块，使得来自至少一个远程无线通信单元的至少一个信号被处理以识别表示输入信号的信号参数 所接收的至少一个信号的功率和到达角度。

公开(公告)号：US20110182335A1

公开(公告)日：2011-07-28

申请号：US12523934

申请日：2007-01-22

Applicant: Patrick J. Pratt ,  Hari Thirumoorthy ,  Conor O'Keeffe

Inventor： Patrick J. Pratt ,  Hari Thirumoorthy ,  Conor O'Keeffe

IPC: H04B17/00

CPC classification number: H03D3/009 ,  H04L27/0014 ,  H04L2027/0016

Abstract: A calibration signal generator for use in a balancing circuit calibration device in a radio receiver, the calibration signal generator comprising: a means of amplifying a clocking signal from a clocking signal generator to provide a first calibration signal; a means of generating a second calibration signal from the clocking signal, the first and second calibration signals being transmissible to a one or more mixing circuits in the balancing circuit calibration device; and a means synchronising the operation of other circuit elements in the balancing circuit calibration device with the clocking signal; characterised in that the clocking signal generator is present in the radio receiver and used therein for other functions.

Abstract translation: 一种用于无线电接收机中的平衡电路校准装置的校准信号发生器，所述校准信号发生器包括：放大来自时钟信号发生器的时钟信号以提供第一校准信号的装置; 从所述时钟信号产生第二校准信号的装置，所述第一和第二校准信号可传输到所述平衡电路校准装置中的一个或多个混合电路; 以及将平衡电路校准装置中的其他电路元件的操作与时钟信号同步的装置; 其特征在于，时钟信号发生器存在于无线电接收机中并在其中用于其它功能。

公开(公告)号：US20110164624A1

公开(公告)日：2011-07-07

申请号：US13061626

申请日：2008-09-05

Applicant: Paul Kelleher ,  Michael O'brien ,  Conor O'keeffe

Inventor： Paul Kelleher ,  Michael O'brien ,  Conor O'keeffe

IPC: H04L12/28

CPC classification number: H04W56/0045 ,  H04B1/40 ,  H04B15/02 ,  H04B2215/067

Abstract: A semiconductor device comprising interface logic for transmitting data bursts across an interface. The interface logic is arranged to transmit bursts of data across the interface such that the start of a burst of data is substantially aligned with a symbol interval (SI) boundary. The interface logic is further arranged to apply an offset to the SI boundary at the start of the burst of data.

Abstract translation: 一种半导体器件，包括用于通过接口传输数据脉冲串的接口逻辑。 接口逻辑被布置成通过接口传输数据脉冲串，使得数据突发的开始基本上与符号间隔（SI）边界对齐。 接口逻辑还被布置为在数据突发的开始处向SI边界应用偏移。

公开(公告)号：US20100111154A1

公开(公告)日：2010-05-06

申请号：US12522043

申请日：2007-01-09

Applicant: Paul Kelleher ,  Diarmuid McSwiney ,  Conor O'Keeffe ,  Emilio Quiroga ,  Samir Soni

Inventor： Paul Kelleher ,  Diarmuid McSwiney ,  Conor O'Keeffe ,  Emilio Quiroga ,  Samir Soni

IPC: H04L27/00 ,  H04B17/00

CPC classification number: H04L7/0338 ,  H04L7/042

Abstract: A wireless communication device comprises a number of sub-systems and clock generation logic arranged to generate at least one clock signal to be applied to the number of sub-systems. One of the number of sub-systems comprises sampling logic for receiving input data and performing initial sampling on an input data bit using multiple separated phases of a clock period of the at least one clock signal applied to the sampling logic thereby producing multiple phase separated sampled outputs of the input data bit. The sampling logic is configured to perform a number of re-sampling operations on the multiple phase separated sampled outputs at a number of intermediate phases thereby producing multiple phase separated intermediate sampled outputs prior to performing a final sample of the multiple phase separated intermediate sampled outputs at a single phase of the at least one clock signal to produce a sampled input data signal.

Abstract translation: 无线通信设备包括多个子系统和时钟生成逻辑，其布置成生成要应用于子系统数量的至少一个时钟信号。 子系统的数量之一包括用于接收输入数据的采样逻辑，并且使用施加到采样逻辑的至少一个时钟信号的时钟周期的多个分离相位对输入数据位执行初始采样，从而产生多相分离采样 输入数据位的输出。 采样逻辑被配置为在多个中间相位的多相分离采样输出上执行多个重采样操作，从而在执行多相分离中间采样输出的最终采样之前产生多相分离中间采样输出 所述至少一个时钟信号的单相以产生采样的输入数据信号。