Abstract:
A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card approximately 151.35 mm or 5.97 inches long provided with about a plurality of contacts of which some are redundant, a plurality of DRAMs, a phase lock loop, a 2 or 32K bit serial EE PROM and a 28 bit and a 1 to 2 register having error correction code (ECC), parity checking, a multi-byte fault reporting circuitry for reading via an independent bus, and real time error lines for determining and reporting both correctable errors and uncorrectable error conditions coupled to the server's memory interface chip and memory controller or processor such that the memory controller sends address and command information to the register via address/command lines together with check bits for error correction purposes to the ECC/Parity register. By providing the module with a fault tolerant address and command bus fault-tolerance and self-healing aspects necessary for autonomic computing systems compatible with industry-standards is realized. The memory module corrects single bit errors on the command or address bus and permits continuous memory operation independent of the existence of these errors and can determine any double bit error condition. The redundant contacts on the module prevents what would otherwise be single points of failure.
Abstract:
A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card approximately 151.35 mm or 5.97 inches long provided with about a plurality of contacts of which some are redundant, a plurality of DRAMs, a phase lock loop, a 2 or 32K bit serial EE PROM and a 28 bit and a 1 to 2 register having error correction code (ECC), parity checking, a multi-byte fault reporting circuitry for reading via an independent bus, and real time error lines for determining and reporting both correctable errors and uncorrectable error conditions coupled to the server's memory interface chip and memory controller or processor such that the memory controller sends address and command information to the register via address/command lines together with check bits for error correction purposes to the ECC/ Parity register. By providing the module with a fault tolerant address and command bus fault-tolerance and self-healing aspects necessary for autonomic computing systems compatible with industry-standards is realized. The memory module corrects single bit errors on the command or address bus and permits continuous memory operation independent of the existence of these errors and can determine any double bit error condition. The redundant contacts on the module prevents what would otherwise be single points of failure.
Abstract:
An apparatus and method for aligning an irregularly shaped object with a contact mask is disclosed. The apparatus includes a means for holding the irregularly shaped object, a means for holding a contact mask, a means for keeping the object and contact mask apart during alignment, means for optically aligning the contact mask to the object, and a means to bring the cube and object together once aligned. A conventional mask alignment tool has been modified to support a clamping fixture which holds the object in a fixed position. It includes a wafer sized disk made of deformable material which permits the edges of the disk to be in contact with the mask, yet when deflected by vacuum pressure will keep the surface of the object away from the contact mask assembly. Upon proper alignment, the vacuum is released and the deformable disk allows the object to cone in contact with the contact mask. In the method of the invention, the process steps include holding an object and contact mask in a spaced relationship from each other, optically aligning the object and contact mask through the holes in the contact mask, and bringing the object and contact mask together once aligned.