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    Biofeedback device for treating obsessive compulsive spectrum disorders (OCSDs)
    2.
    发明授权
    Biofeedback device for treating obsessive compulsive spectrum disorders (OCSDs) 失效
    用于治疗强迫性强迫症（OCSD）的生物反馈装置

    公开(公告)号：US06762687B2

    公开(公告)日：2004-07-13

    申请号：US10175934

    申请日：2002-06-20

    Applicant: David Perlman

    Inventor： David Perlman

    IPC: G08B2300

    CPC classification number: G08B23/00

    Abstract: A biofeedback device for treatment of certain obsessive compulsive spectrum and habit disorders including trichotillomania (hair pulling), onychophagia (nail biting), thumb-sucking, skin-scratching (dermatillomania) and certain other self-inflicted harm, includes a sensing element and triggering device, both worn on various parts of the body, depending upon the particular characteristics of an individual's disorder. The biofeedback device is able to sense the movement of one body part relative to another and set off an alarm mechanism prior to contact, assisting the patient in avoiding the destructive behavior.

    Abstract translation: 用于治疗某些强迫性强迫症和习惯障碍（包括拔毛症），精神病（指甲咬伤），拇指吸吮，皮肤搔痒（皮肤搔痒症）和某些其他自身伤害的生物反馈装置包括感测元件和触发 装置，均佩戴在身体的各个部位上，这取决于个体病症的特征。 生物反馈装置能够感测一个身体部分相对于另一个身体部分的运动，并在接触之前发出报警机构，从而帮助患者避免破坏行为。

    High reliability memory module with a fault tolerant address and command bus
    4.
    发明申请
    High reliability memory module with a fault tolerant address and command bus 有权
    高可靠性存储器模块，具有容错地址和命令总线

    公开(公告)号：US20060236201A1

    公开(公告)日：2006-10-19

    申请号：US11406669

    申请日：2006-04-20

    Applicant: Kevin Gower ,  Bruce Hazelzet ,  Mark Kellogg ,  David Perlman

    Inventor： Kevin Gower ,  Bruce Hazelzet ,  Mark Kellogg ,  David Perlman

    IPC: H03M13/00

    CPC classification number: H05K1/117 ,  G06F11/1044 ,  G11C5/04 ,  G11C2029/0409 ,  H05K2201/09145 ,  H05K2203/167

    Abstract: A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card approximately 151.35 mm or 5.97 inches long provided with about a plurality of contacts of which some are redundant, a plurality of DRAMs, a phase lock loop, a 2 or 32K bit serial EE PROM and a 28 bit and a 1 to 2 register having error correction code (ECC), parity checking, a multi-byte fault reporting circuitry for reading via an independent bus, and real time error lines for determining and reporting both correctable errors and uncorrectable error conditions coupled to the server's memory interface chip and memory controller or processor such that the memory controller sends address and command information to the register via address/command lines together with check bits for error correction purposes to the ECC/Parity register. By providing the module with a fault tolerant address and command bus fault-tolerance and self-healing aspects necessary for autonomic computing systems compatible with industry-standards is realized. The memory module corrects single bit errors on the command or address bus and permits continuous memory operation independent of the existence of these errors and can determine any double bit error condition. The redundant contacts on the module prevents what would otherwise be single points of failure.

    Abstract translation: 具有容错地址和命令总线的高可靠性双列直插式存储器模块，用于服务器。 存储器模块是大约151.35mm或5.97英寸长的卡，其具有大约多个触点，其中一些是冗余的，多个DRAM，锁相环，2或32K位串行EE PROM和28位和 具有纠错码（ECC），奇偶校验，用于经由独立总线读取的多字节故障报告电路的1至2寄存器和用于确定和报告耦合到服务器存储器的可纠正错误和不可校正错误状况的实时错误行 接口芯片和存储器控制器或处理器，使得存储器控制器通过地址/命令行将地址和命令信息与用于纠错目的的校验位一起发送到ECC /奇偶校验寄存器。 通过为模块提供与行业标准兼容的自主计算系统所需的容错地址和命令总线容错和自修复方面。 存储器模块纠正命令或地址总线上的单位错误，并允许连续存储器操作，而不管这些错误是否存在，并且可以确定任何双位错误条件。 模块上的冗余联系人可防止出现单点故障。

    HIGH RELIABILITY MEMORY MODULE WITH A FAULT TOLERANT ADDRESS AND COMMAND BUS
    8.
    发明申请
    HIGH RELIABILITY MEMORY MODULE WITH A FAULT TOLERANT ADDRESS AND COMMAND BUS 有权

    公开(公告)号：US20070204201A1

    公开(公告)日：2007-08-30

    申请号：US11741319

    申请日：2007-04-27

    Applicant: Kevin Gower ,  Bruce Hazelzet ,  Mark Kellogg ,  David Perlman

    Inventor： Kevin Gower ,  Bruce Hazelzet ,  Mark Kellogg ,  David Perlman

    IPC: G11C29/00

    CPC classification number: H05K1/117 ,  G06F11/1044 ,  G11C5/04 ,  G11C2029/0409 ,  H05K2201/09145 ,  H05K2203/167

    Abstract: A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card approximately 151.35 mm or 5.97 inches long provided with about a plurality of contacts of which some are redundant, a plurality of DRAMs, a phase lock loop, a 2 or 32K bit serial EE PROM and a 28 bit and a 1 to 2 register having error correction code (ECC), parity checking, a multi-byte fault reporting circuitry for reading via an independent bus, and real time error lines for determining and reporting both correctable errors and uncorrectable error conditions coupled to the server's memory interface chip and memory controller or processor such that the memory controller sends address and command information to the register via address/command lines together with check bits for error correction purposes to the ECC/ Parity register. By providing the module with a fault tolerant address and command bus fault-tolerance and self-healing aspects necessary for autonomic computing systems compatible with industry-standards is realized. The memory module corrects single bit errors on the command or address bus and permits continuous memory operation independent of the existence of these errors and can determine any double bit error condition. The redundant contacts on the module prevents what would otherwise be single points of failure.

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