公开(公告)号：US20060190780A1

公开(公告)日：2006-08-24

申请号：US11406717

申请日：2006-04-20

申请人： Kevin Gower ,  Bruce Hazelzet ,  Mark Kellogg ,  David Perlman

发明人： Kevin Gower ,  Bruce Hazelzet ,  Mark Kellogg ,  David Perlman

IPC分类号： G11C29/00

CPC分类号： H05K1/117 ,  G06F11/1044 ,  G11C5/04 ,  G11C2029/0409 ,  H05K2201/09145 ,  H05K2203/167

摘要： A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card approximately 151.35 mm or 5.97 inches long provided with about a plurality of contacts of which some are redundant, a plurality of DRAMs, a phase lock loop, a 2 or 32K bit serial EE PROM and a 28 bit and a 1 to 2 register having error correction code (ECC), parity checking, a multi-byte fault reporting circuitry for reading via an independent bus, and real time error lines for determining and reporting both correctable errors and uncorrectable error conditions coupled to the server's memory interface chip and memory controller or processor such that the memory controller sends address and command information to the register via address/command lines together with check bits for error correction purposes to the ECC/Parity register. By providing the module with a fault tolerant address and command bus fault-tolerance and self-healing aspects necessary for autonomic computing systems compatible with industry-standards is realized. The memory module corrects single bit errors on the command or address bus and permits continuous memory operation independent of the existence of these errors and can determine any double bit error condition. The redundant contacts on the module prevents what would otherwise be single points of failure.

公开(公告)号：US20070204201A1

公开(公告)日：2007-08-30

申请号：US11741319

申请日：2007-04-27

申请人： Kevin Gower ,  Bruce Hazelzet ,  Mark Kellogg ,  David Perlman

发明人： Kevin Gower ,  Bruce Hazelzet ,  Mark Kellogg ,  David Perlman

IPC分类号： G11C29/00

CPC分类号： H05K1/117 ,  G06F11/1044 ,  G11C5/04 ,  G11C2029/0409 ,  H05K2201/09145 ,  H05K2203/167

摘要： A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card approximately 151.35 mm or 5.97 inches long provided with about a plurality of contacts of which some are redundant, a plurality of DRAMs, a phase lock loop, a 2 or 32K bit serial EE PROM and a 28 bit and a 1 to 2 register having error correction code (ECC), parity checking, a multi-byte fault reporting circuitry for reading via an independent bus, and real time error lines for determining and reporting both correctable errors and uncorrectable error conditions coupled to the server's memory interface chip and memory controller or processor such that the memory controller sends address and command information to the register via address/command lines together with check bits for error correction purposes to the ECC/ Parity register. By providing the module with a fault tolerant address and command bus fault-tolerance and self-healing aspects necessary for autonomic computing systems compatible with industry-standards is realized. The memory module corrects single bit errors on the command or address bus and permits continuous memory operation independent of the existence of these errors and can determine any double bit error condition. The redundant contacts on the module prevents what would otherwise be single points of failure.

公开(公告)号：US20060236201A1

公开(公告)日：2006-10-19

申请号：US11406669

申请日：2006-04-20

申请人： Kevin Gower ,  Bruce Hazelzet ,  Mark Kellogg ,  David Perlman

发明人： Kevin Gower ,  Bruce Hazelzet ,  Mark Kellogg ,  David Perlman

IPC分类号： H03M13/00

CPC分类号： H05K1/117 ,  G06F11/1044 ,  G11C5/04 ,  G11C2029/0409 ,  H05K2201/09145 ,  H05K2203/167

摘要： A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card approximately 151.35 mm or 5.97 inches long provided with about a plurality of contacts of which some are redundant, a plurality of DRAMs, a phase lock loop, a 2 or 32K bit serial EE PROM and a 28 bit and a 1 to 2 register having error correction code (ECC), parity checking, a multi-byte fault reporting circuitry for reading via an independent bus, and real time error lines for determining and reporting both correctable errors and uncorrectable error conditions coupled to the server's memory interface chip and memory controller or processor such that the memory controller sends address and command information to the register via address/command lines together with check bits for error correction purposes to the ECC/Parity register. By providing the module with a fault tolerant address and command bus fault-tolerance and self-healing aspects necessary for autonomic computing systems compatible with industry-standards is realized. The memory module corrects single bit errors on the command or address bus and permits continuous memory operation independent of the existence of these errors and can determine any double bit error condition. The redundant contacts on the module prevents what would otherwise be single points of failure.

摘要翻译： 具有容错地址和命令总线的高可靠性双列直插式存储器模块，用于服务器。 存储器模块是大约151.35mm或5.97英寸长的卡，其具有大约多个触点，其中一些是冗余的，多个DRAM，锁相环，2或32K位串行EE PROM和28位和 具有纠错码（ECC），奇偶校验，用于经由独立总线读取的多字节故障报告电路的1至2寄存器和用于确定和报告耦合到服务器存储器的可纠正错误和不可校正错误状况的实时错误行 接口芯片和存储器控制器或处理器，使得存储器控制器通过地址/命令行将地址和命令信息与用于纠错目的的校验位一起发送到ECC /奇偶校验寄存器。 通过为模块提供与行业标准兼容的自主计算系统所需的容错地址和命令总线容错和自修复方面。 存储器模块纠正命令或地址总线上的单位错误，并允许连续存储器操作，而不管这些错误是否存在，并且可以确定任何双位错误条件。 模块上的冗余联系人可防止出现单点故障。

公开(公告)号：US20070250756A1

公开(公告)日：2007-10-25

申请号：US11406718

申请日：2006-04-20

申请人： Kevin Gower ,  Bruce Hazelzet ,  Mark Kellogg ,  David Perlman

发明人： Kevin Gower ,  Bruce Hazelzet ,  Mark Kellogg ,  David Perlman

IPC分类号： G11C29/00

CPC分类号： H05K1/117 ,  G06F11/1044 ,  G11C5/04 ,  G11C2029/0409 ,  H05K2201/09145 ,  H05K2203/167

摘要： A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card approximately 151.35 mm or 5.97 inches long provided with about a plurality of contacts of which some are redundant, a plurality of DRAMs, a phase lock loop, a 2 or 32K bit serial EE PROM and a 28 bit and a 1 to 2 register having error correction code (ECC), parity checking, a multi-byte fault reporting circuitry for reading via an independent bus, and real time error lines for determining and reporting both correctable errors and uncorrectable error conditions coupled to the server's memory interface chip and memory controller or processor such that the memory controller sends address and command information to the register via address/command lines together with check bits for error correction purposes to the ECC/Parity register. By providing the module with a fault tolerant address and command bus fault-tolerance and self-healing aspects necessary for autonomic computing systems compatible with industry-standards is realized. The memory module corrects single bit errors on the command or address bus and permits continuous memory operation independent of the existence of these errors and can determine any double bit error condition. The redundant contacts on the module prevents what would otherwise be single points of failure.

摘要翻译： 具有容错地址和命令总线的高可靠性双列直插式存储器模块，用于服务器。 存储器模块是大约151.35mm或5.97英寸长的卡，其具有大约多个触点，其中一些是冗余的，多个DRAM，锁相环，2或32K位串行EE PROM和28位和 具有纠错码（ECC），奇偶校验，用于经由独立总线读取的多字节故障报告电路的1至2寄存器和用于确定和报告耦合到服务器存储器的可纠正错误和不可校正错误状况的实时错误行 接口芯片和存储器控制器或处理器，使得存储器控制器通过地址/命令行将地址和命令信息与用于纠错目的的校验位一起发送到ECC /奇偶校验寄存器。 通过为模块提供与行业标准兼容的自主计算系统所需的容错地址和命令总线容错和自修复方面。 存储器模块纠正命令或地址总线上的单位错误，并允许连续存储器操作，而不管这些错误是否存在，并且可以确定任何双位错误条件。 模块上的冗余联系人可防止出现单点故障。

公开(公告)号：US20070204200A1

公开(公告)日：2007-08-30

申请号：US11741314

申请日：2007-04-27

申请人： Kevin Gower ,  Bruce Hazelzet ,  Mark Kellogg ,  David Perlman

发明人： Kevin Gower ,  Bruce Hazelzet ,  Mark Kellogg ,  David Perlman

IPC分类号： H05K7/00

CPC分类号： H05K1/117 ,  G06F11/1044 ,  G11C5/04 ,  G11C2029/0409 ,  H05K2201/09145 ,  H05K2203/167

摘要： A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card approximately 151.35 mm or 5.97 inches long provided with about a plurality of contacts of which some are redundant, a plurality of DRAMs, a phase lock loop, a 2 or 32K bit serial EE PROM and a 28 bit and a 1 to 2 register having error correction code (ECC), parity checking, a multi-byte fault reporting circuitry for reading via an independent bus, and real time error lines for determining and reporting both correctable errors and uncorrectable error conditions coupled to the server's memory interface chip and memory controller or processor such that the memory controller sends address and command information to the register via address/command lines together with check bits for error correction purposes to the ECC/ Parity register. By providing the module with a fault tolerant address and command bus fault-tolerance and self-healing aspects necessary for autonomic computing systems compatible with industry-standards is realized. The memory module corrects single bit errors on the command or address bus and permits continuous memory operation independent of the existence of these errors and can determine any double bit error condition. The redundant contacts on the module prevents what would otherwise be single points of failure.

摘要翻译： 具有容错地址和命令总线的高可靠性双列直插式存储器模块，用于服务器。 存储器模块是大约151.35mm或5.97英寸长的卡，其具有大约多个触点，其中一些是冗余的，多个DRAM，锁相环，2或32K位串行EE PROM和28位和 具有纠错码（ECC），奇偶校验，用于经由独立总线读取的多字节故障报告电路的1至2寄存器和用于确定和报告耦合到服务器存储器的可纠正错误和不可校正错误状况的实时错误行 接口芯片和存储器控制器或处理器，使得存储器控制器通过地址/命令行将地址和命令信息与用于纠错目的的校验位一起发送到ECC /奇偶校验寄存器。 通过为模块提供与行业标准兼容的自主计算系统所需的容错地址和命令总线容错和自修复方面。 存储器模块纠正命令或地址总线上的单位错误，并允许连续存储器操作，而不管这些错误是否存在，并且可以确定任何双位错误条件。 模块上的冗余联系人可防止出现单点故障。

公开(公告)号：US20060242541A1

公开(公告)日：2006-10-26

申请号：US11406719

申请日：2006-04-20

申请人： Kevin Gower ,  Bruce Hazelzet ,  Mark Kellogg ,  David Perhnan

发明人： Kevin Gower ,  Bruce Hazelzet ,  Mark Kellogg ,  David Perhnan

IPC分类号： G11C29/00

CPC分类号： H05K1/117 ,  G06F11/1044 ,  G11C5/04 ,  G11C2029/0409 ,  H05K2201/09145 ,  H05K2203/167

摘要： A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card approximately 151.35 mm or 5.97 inches long provided with about a plurality of contacts of which some are redundant, a plurality of DRAMs, a phase lock loop, a 2 or 32 K bit serial EE PROM and a 28 bit and a 1 to 2 register having error correction code (ECC), parity checking, a multi-byte fault reporting circuitry for reading via an independent bus, and real time error lines for determining and reporting both correctable errors and uncorrectable error conditions coupled to the server's memory interface chip and memory controller or processor such that the memory controller sends address and command information to the register via address/command lines together with check bits for error correction purposes to the ECC/Parity register. By providing the module with a fault tolerant address and command bus fault-tolerence and self-healing aspects necessary for autonomic computing systems compatible with industry-standards is realized. The memory module corrects single bit errors on the command or address bus and permits continuous memory operation independent of the existence of these errors and can determine any double bit error condition. The redundant contacts on the module prevents what would otherwise be single points of failure.

摘要翻译： 具有容错地址和命令总线的高可靠性双列直插式存储器模块，用于服务器。 存储器模块是大约151.35mm或5.97英寸长的卡，其具有大约多个触点，其中一些是冗余的，多个DRAM，锁相环，2或32K位串行EE PROM和28位 具有纠错码（ECC）的1至2寄存器，奇偶校验，用于经由独立总线读取的多字节故障报告电路以及用于确定和报告可纠正错误的实时错误线以及耦合到服务器 存储器接口芯片和存储器控制器或处理器，使得存储器控制器通过地址/命令行与地址/命令行一起发送地址和命令信息以及用于纠错目的的校验位给ECC /奇偶校验寄存器。 通过为模块提供与行业标准兼容的自主计算系统所需的容错地址和命令总线故障修复和自修复方面。 存储器模块纠正命令或地址总线上的单位错误，并允许连续存储器操作，而不管这些错误是否存在，并且可以确定任何双位错误条件。 模块上的冗余联系人可防止出现单点故障。

公开(公告)号：US20050108468A1

公开(公告)日：2005-05-19

申请号：US10707053

申请日：2003-11-18

申请人： Bruce Hazelzet ,  Mark Kellogg ,  Darcie Rankin

发明人： Bruce Hazelzet ,  Mark Kellogg ,  Darcie Rankin

IPC分类号： G06F12/00 ,  G06F12/16 ,  G11C11/401 ,  G11C11/4063

CPC分类号： G06F13/4243 ,  G11C7/1078 ,  G11C7/109

摘要： A memory system having a plurality of DRAMs which are selectively provided non-inverted or inverted signals. The DRAMs have the ability to accept non-inverted or inverted address/command signals from a register that drives a plurality of signals simultaneously. The system includes DRAM receivers with programmable input polarity and a register with programmable output polarity.

摘要翻译： 具有选择性地提供非反相或反相信号的多个DRAM的存储器系统。 DRAM具有从同时驱动多个信号的寄存器接受非反相或反相地址/命令信号的能力。 该系统包括具有可编程输入极性的DRAM接收器和具有可编程输出极性的寄存器。

公开(公告)号：US20060036826A1

公开(公告)日：2006-02-16

申请号：US10903182

申请日：2004-07-30

申请人： Timothy Dell ,  Kevin Gower ,  Kevin Kark ,  Mark Kellogg ,  Warren Maule

发明人： Timothy Dell ,  Kevin Gower ,  Kevin Kark ,  Mark Kellogg ,  Warren Maule

IPC分类号： G06F12/00

CPC分类号： G06F13/4243 ,  G06F13/1684

摘要： A memory subsystem for providing a bus speed multiplier. The memory subsystem includes one or more memory modules operating at a memory module data rate. The memory subsystem also includes a memory controller and one or more memory busses. The memory busses operate at four times the memory module data rate. The memory controller and the memory modules are interconnected by a packetized multi-transfer interface via the memory busses.

摘要翻译： 用于提供总线速度倍增器的存储器子系统。 存储器子系统包括以存储器模块数据速率操作的一个或多个存储器模块。 存储器子系统还包括存储器控制器和一个或多个存储器总线。 存储器总线的操作是内存模块数据速率的四倍。 存储器控制器和存储器模块通过分组化的多传输接口经由存储器总线互连。

公开(公告)号：US20060095671A1

公开(公告)日：2006-05-04

申请号：US10977846

申请日：2004-10-29

申请人： Kevin Gower ,  Mark Kellogg ,  Warren Maule ,  Thomas Smith ,  Robert Tremaine

发明人： Kevin Gower ,  Mark Kellogg ,  Warren Maule ,  Thomas Smith ,  Robert Tremaine

IPC分类号： G06F13/00

CPC分类号： G06F13/1684 ,  G06F12/0802 ,  G06F2212/401

摘要： A cascaded interconnect system including a memory controller, one or more memory modules, an upstream memory bus and a downstream memory bus. The one or more memory modules include a first memory module with cache data. The memory modules and the memory controller are interconnected by a packetized multi-transfer interface via the downstream memory bus and the upstream memory bus. The first memory module and the memory controller are in direct communication via the upstream memory bus and the downstream memory bus.

公开(公告)号：US20080016280A1

公开(公告)日：2008-01-17

申请号：US11772922

申请日：2007-07-03

申请人： Kevin Gower ,  Mark Kellogg ,  Warren Maule ,  Thomas Smith ,  Robert Tremaine

发明人： Kevin Gower ,  Mark Kellogg ,  Warren Maule ,  Thomas Smith ,  Robert Tremaine

IPC分类号： G06F12/08

CPC分类号： G06F13/1684 ,  G06F12/0802 ,  G06F2212/401

摘要： A cascaded interconnect system including a memory controller, one or more memory modules, an upstream memory bus and a downstream memory bus. The one or more memory modules include a first memory module with cache data. The memory modules and the memory controller are interconnected by a packetized multi-transfer interface via the downstream memory bus and the upstream memory bus. The first memory module and the memory controller are in direct communication via the upstream memory bus and the downstream memory bus.

摘要翻译： 包括存储器控制器，一个或多个存储器模块，上游存储器总线和下游存储器总线的级联互连系统。 一个或多个存储器模块包括具有高速缓存数据的第一存储器模块。 存储器模块和存储器控制器通过分组化的多传输接口经由下游存储器总线和上游存储器总线互连。 第一存储器模块和存储器控制器经由上游存储器总线和下游存储器总线直接通信。