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公开(公告)号：US07456664B2
公开(公告)日：2008-11-25
申请号：US10581786
申请日：2003-12-10
IPC分类号： H03L7/06
CPC分类号： H03L7/0812
摘要： The invention discloses a delay-locked loop circuit with input means for a signal that is to be delayed, the input means comprising means for splitting the input signal into a first and a second branch. The signal in the first branch is connected to a component for delaying the signal, and the signal in the second branch is used as a non-delayed reference for the delay caused by the delay component in the first branch. The delay component is a passive tunable delay line, and the circuit comprises tuning means for the tunable delay line, the tuning means being affected by said reference signal, and the first branch comprises output means for outputting a delayed signal with a chosen phase delay. Suitably, the delay component is continuously tunable, for example a tunable ferroelectric delay line.
摘要翻译： 本发明公开了一种具有用于待延迟的信号的输入装置的延迟锁定环路，输入装置包括用于将输入信号分成第一和第二分支的装置。 第一分支中的信号连接到用于延迟信号的分量，并且第二分支中的信号用作由第一分支中的延迟分量引起的延迟的非延迟参考。 所述延迟部件是无源可调谐延迟线，并且所述电路包括用于所述可调谐延迟线的调谐装置，所述调谐装置受所述参考信号的影响，并且所述第一分支包括用于输出具有所选相位延迟的延迟信号的输出装置。 适当地，延迟分量是可连续调节的，例如可调铁电延迟线。
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公开(公告)号：US20080055023A1
公开(公告)日：2008-03-06
申请号：US11573312
申请日：2004-07-06
摘要： The invention discloses a tuneable resonator (100, 200, 300, 500, 600, 700, 900) with a substrate layer (140, 260, 360, 560, 660, 960), which substrate layer supports a structure with a first electrode (130, 240, 350, 550, 650). In connection to the first electrode there is arranged a layer (120, 230, 330, 530, 630, 930) of a material which can be brought to resonate. The resonator further comprises a second electrode (110, 210, 310, 510, 610, 710, 910) arranged in connection to said material which can be brought to resonate, and the material which can be brought to resonate is a ferroelectric material. The ferroelectric material is brought into resonance by applying an electrical field (DC, AC) between the first and the second electrode, the tuning being achieved by varying the electrical field.
摘要翻译： 本发明公开了一种具有衬底层（140,260,360,560,660,960）的可调谐谐振器（100,200,300,500,600,700,900），该衬底层支撑具有第一电极（ 130,240,350,550,650）。 与第一电极相连，布置有能够引起共振的材料层（120,230,330,530,630,930）。 所述谐振器还包括与所述材料相连接设置的第二电极（110,210,310,510,610,710,910），所述第二电极可被引起谐振，并且可以引起谐振的材料是铁电材料。 铁电材料通过在第一和第二电极之间施加电场（DC，AC）而进入共振，通过改变电场来实现调谐。
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23.发明授权公开(公告)号：US06903614B2
公开(公告)日：2005-06-07
申请号：US10751104
申请日：2004-01-05
申请人： Harald Jacobsson , Bertil Hansson
发明人： Harald Jacobsson , Bertil Hansson
CPC分类号： H03B5/1212 , H03B5/1231
摘要： A method of locking a first differential oscillator with a second differential oscillator and a circuit and an arrangement therefor. The method comprises AC coupling a fundamental frequency AC-ground of the first differential oscillator with a fundamental frequency AC-ground of the second differential oscillator.
摘要翻译： 一种用第二差分振荡器锁定第一差分振荡器的方法及其电路及其配置。 该方法包括将第一差分振荡器的基频AC地和AC耦合到第二差分振荡器的基频AC地。
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公开(公告)号：US06504109B1
公开(公告)日：2003-01-07
申请号：US09605636
申请日：2000-06-28
申请人： Omid Aval , Håkan Berg , Spartak Gevorgian , Bertil Hansson , Harald Jacobsson , Thomas Lewin
发明人： Omid Aval , Håkan Berg , Spartak Gevorgian , Bertil Hansson , Harald Jacobsson , Thomas Lewin
IPC分类号： H01R909
摘要： A printed circuit (1) on a lossy substrate (2) has been provided whereby intermediate structures (11, 12, 17, 18) under the top layer strips (5) have been formed having a width being (d2) smaller than the width (w) of the strip. The intermediate structures (11, 12, 17, 18) are particular well suited for inductors (9) on silicon substrates and result in a considerable increase in the Q-factor of the inductor at microwave frequencies.
摘要翻译： 已经提供了一种在有损耗的基板（2）上的印刷电路（1），由此已经形成了顶层条（5）下方的中间结构（11,12,17,18），其宽度（d2）小于宽度 （w）。 中间结构（11,12,17,18）特别适用于硅衬底上的电感器（9），并且导致微波频率下电感器的Q因数的显着增加。
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公开(公告)号：US08249541B2
公开(公告)日：2012-08-21
申请号：US12094310
申请日：2005-11-23
申请人： Mingquan Bao , Harald Jacobsson
发明人： Mingquan Bao , Harald Jacobsson
IPC分类号： H04B1/28
CPC分类号： H03D7/125
摘要： The present invention relates to a sub-harmonically pumped conversion mixer arrangement that includes a transistor arrangement and transistor terminals for application of a local oscillator, LO-, signal and application of a radio frequency, RF-, signal and for extraction of a mixed intermediate frequency, IF-, signal. The transistor arrangement includes at least one NMOS transistor and at least one PMOS transistor. The drain of the at least one NMOS transistor is interconnected with the drain of the at least one PMOS transistor, and in that the gate of the at least one PMOS transistor is interconnected with the gate of the at least one NMOS transistor.
摘要翻译： 本发明涉及一种亚谐波抽运转换混频器装置，其包括用于施加本地振荡器的晶体管布置和晶体管端子，LO-，信号和射频，RF-信号的应用，以及用于提取混合中间体 频率，IF-信号。 晶体管装置包括至少一个NMOS晶体管和至少一个PMOS晶体管。 所述至少一个NMOS晶体管的漏极与所述至少一个PMOS晶体管的漏极互连，并且所述至少一个PMOS晶体管的栅极与所述至少一个NMOS晶体管的栅极互连。
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公开(公告)号：US20090128245A1
公开(公告)日：2009-05-21
申请号：US12088219
申请日：2005-09-27
申请人： Lars Aspemyr , Harald Jacobsson
发明人： Lars Aspemyr , Harald Jacobsson
IPC分类号： H03B5/00
CPC分类号： H03B5/1215 , H03B5/1228
摘要： The present invention relates to an oscillator circuit having a resonant element, an active element, a feedback loop, and an additional loop comprising a phase shifting element.
摘要翻译： 本发明涉及一种具有谐振元件，有源元件，反馈回路和包括相移元件的附加回路的振荡器电路。
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公开(公告)号：US20080287088A1
公开(公告)日：2008-11-20
申请号：US12094310
申请日：2005-11-23
申请人： Mingquan Bao , Harald Jacobsson
发明人： Mingquan Bao , Harald Jacobsson
IPC分类号： H04B1/28
CPC分类号： H03D7/125
摘要： The present invention relates to a sub-harmonically pumped conversion mixer arrangement comprising a transistor arrangement and transistor terminals for application of a local oscillator, LO-, signal and application of a radio frequency, RF-, signal and for extraction of a mixed intermediate frequency, IF-, signal. The transistor arrangement comprises at least one NMOS transistor and at least one PMOS transistor. The drain of said at least one NMOS transistor is interconnected with the drain of said at least one PMOS transistor, and in that the gate of said at least one PMOS transistor is interconnected with the gate of said at least one NMOS transistor.
摘要翻译： 本发明涉及一种亚谐波抽运转换混频器装置，其包括晶体管装置和用于施加本地振荡器的晶体管端子，LO-，信号和射频，RF-信号的应用，以及用于提取混合中频 ，IF-，信号。 晶体管布置包括至少一个NMOS晶体管和至少一个PMOS晶体管。 所述至少一个NMOS晶体管的漏极与所述至少一个PMOS晶体管的漏极互连，并且所述至少一个PMOS晶体管的栅极与所述至少一个NMOS晶体管的栅极互连。
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公开(公告)号：US07414443B2
公开(公告)日：2008-08-19
申请号：US10581787
申请日：2003-12-10
申请人： Harald Jacobsson , Thomas Lewin
发明人： Harald Jacobsson , Thomas Lewin
IPC分类号： H03B19/00
CPC分类号： G06F7/68
摘要： A device is provided for multiplying the pulse frequency of a pulse train signal. The device includes input means for the signal and means for accessing the signal at points with a predetermined phase difference between them. The device additionally comprises means at a first level for combining accessed signal pairs, with one and the same phase distance within all the combined pairs, the output from each first level combining means being a pulse train. The device additionally comprises combining means at a second level for combining the pulse trains from the first level, and the combining means at the first level are such that the pulses in their output pulse trains have rise flanks which always coincide with the rise flank of the first signal in the combined accessed signal pairs, and fall flanks which always coincide with the fall flanks of the second signal in said pair.
摘要翻译： 提供了用于乘以脉冲串信号的脉冲频率的装置。 该装置包括用于信号的输入装置和用于在它们之间具有预定相位差的点访问信号的装置。 该装置还包括用于组合可访问信号对的第一级的装置，在所有组合对内具有相同的相位距离，每个第一级组合装置的输出是脉冲串。 该装置还包括用于组合来自第一电平的脉冲串的第二电平的组合装置，并且在第一电平处的组合装置使得它们的输出脉冲串中的脉冲具有总是与所述第一电平的上升侧面重合的上升侧面 组合的访问信号对中的第一信号和总是与所述对中的第二信号的下降侧面重合的下降侧面。
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公开(公告)号：US20070139089A1
公开(公告)日：2007-06-21
申请号：US10581786
申请日：2003-12-10
IPC分类号： H03L7/06
CPC分类号： H03L7/0812
摘要： The invention discloses a delay-locked loop circuit with input means for a signal that is to be delayed, the input means comprising means for splitting the input signal into a first and a second branch. The signal in the first branch is connected to a component for delaying the signal, and the signal in the second branch is used as a non-delayed reference for the delay caused by the delay component in the first branch. The delay component is a passive tunable delay line, and the circuit comprises tuning means for the tunable delay line, the tuning means being affected by said reference signal, and the first branch comprises output means for outputting a delayed signal with a chosen phase delay. Suitably, the delay component is continuously tunable, for example a tunable ferroelectric delay line.
摘要翻译： 本发明公开了一种具有用于待延迟的信号的输入装置的延迟锁定环路，输入装置包括用于将输入信号分成第一和第二分支的装置。 第一分支中的信号连接到用于延迟信号的分量，并且第二分支中的信号用作由第一分支中的延迟分量引起的延迟的非延迟参考。 所述延迟部件是无源可调谐延迟线，并且所述电路包括用于所述可调谐延迟线的调谐装置，所述调谐装置受所述参考信号的影响，并且所述第一分支包括用于输出具有所选相位延迟的延迟信号的输出装置。 适当地，延迟分量是可连续调节的，例如可调铁电延迟线。
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