Micro-strip circuit for loss reduction
    1.
    发明授权
    Micro-strip circuit for loss reduction 有权
    微带电路用于减少损耗

    公开(公告)号:US06504109B1

    公开(公告)日:2003-01-07

    申请号:US09605636

    申请日:2000-06-28

    IPC分类号: H01R909

    CPC分类号: H01P3/081 H01P3/08

    摘要: A printed circuit (1) on a lossy substrate (2) has been provided whereby intermediate structures (11, 12, 17, 18) under the top layer strips (5) have been formed having a width being (d2) smaller than the width (w) of the strip. The intermediate structures (11, 12, 17, 18) are particular well suited for inductors (9) on silicon substrates and result in a considerable increase in the Q-factor of the inductor at microwave frequencies.

    摘要翻译: 已经提供了一种在有损耗的基板(2)上的印刷电路(1),由此已经形成了顶层条(5)下方的中间结构(11,12,17,18),其宽度(d2)小于宽度 (w)。 中间结构(11,12,17,18)特别适用于硅衬底上的电感器(9),并且导致微波频率下电感器的Q因数的显着增加。

    Tuneable ferroelectric delay line having mirror image conductors
    2.
    发明授权
    Tuneable ferroelectric delay line having mirror image conductors 失效
    具有镜像导体的调谐铁电延迟线

    公开(公告)号:US07642883B2

    公开(公告)日:2010-01-05

    申请号:US10586139

    申请日:2004-03-09

    IPC分类号: H01P1/18

    CPC分类号: H01P9/04 H01P9/006

    摘要: A tunable electromagnetic delay line, comprising a first conductor with a first main direction of extension. The first conductor is arranged on top of a non-conducting substrate. The delay line additionally comprises a layer of a ferroelectric material with first and second main surfaces. The layer separates the first conductor and the substrate. The delay line also comprises a second conductor with a second main direction of extension, with the first and second main directions of extensions essentially coinciding with each other, and with the first and second conductors being each other's mirror image with respect to an imagined line in the center of the delay line along the first and second main directions of extension. The tuning is accomplished by applying a voltage between said first and second conductors.

    摘要翻译: 一种可调电磁延迟线,包括具有第一主延伸方向的第一导体。 第一导体布置在非导电衬底的顶部。 延迟线还包括具有第一和第二主表面的铁电材料层。 该层分离第一导体和基底。 延迟线还包括具有第二主延伸方向的第二导体,其中延伸部的第一和第二主方向基本上彼此重合,并且第一和第二导体相对于想象线彼此相对于镜像 沿着第一和第二主要延伸方向的延迟线的中心。 通过在所述第一和第二导体之间施加电压来实现调谐。

    Delay locked loop with precision contolled delay
    3.
    发明申请
    Delay locked loop with precision contolled delay 有权
    延迟锁定环路,具有精确的等距延迟

    公开(公告)号:US20070139089A1

    公开(公告)日:2007-06-21

    申请号:US10581786

    申请日:2003-12-10

    IPC分类号: H03L7/06

    CPC分类号: H03L7/0812

    摘要: The invention discloses a delay-locked loop circuit with input means for a signal that is to be delayed, the input means comprising means for splitting the input signal into a first and a second branch. The signal in the first branch is connected to a component for delaying the signal, and the signal in the second branch is used as a non-delayed reference for the delay caused by the delay component in the first branch. The delay component is a passive tunable delay line, and the circuit comprises tuning means for the tunable delay line, the tuning means being affected by said reference signal, and the first branch comprises output means for outputting a delayed signal with a chosen phase delay. Suitably, the delay component is continuously tunable, for example a tunable ferroelectric delay line.

    摘要翻译: 本发明公开了一种具有用于待延迟的信号的输入装置的延迟锁定环路,输入装置包括用于将输入信号分成第一和第二分支的装置。 第一分支中的信号连接到用于延迟信号的分量,并且第二分支中的信号用作由第一分支中的延迟分量引起的延迟的非延迟参考。 所述延迟部件是无源可调谐延迟线,并且所述电路包括用于所述可调谐延迟线的调谐装置,所述调谐装置受所述参考信号的影响,并且所述第一分支包括用于输出具有所选相位延迟的延迟信号的输出装置。 适当地,延迟分量是可连续调节的,例如可调铁电延迟线。

    Oscillator circuit with tuneable signal delay means
    4.
    发明申请
    Oscillator circuit with tuneable signal delay means 有权
    具有可调信号延迟装置的振荡电路

    公开(公告)号:US20070126511A1

    公开(公告)日:2007-06-07

    申请号:US10581788

    申请日:2003-12-10

    IPC分类号: H03L7/00

    CPC分类号: H03B5/24 H03L7/0812

    摘要: The invention discloses an oscillator circuit (100, 200, 300, 400), comprising an oscillating element (110, 210, 310, 410) and output means (115, 215, 315, 415) for outputting an oscillation frequency from the oscillating circuit. The circuit further comprises a signal delay means (120, 220, 320, 420) which is arranged in series with the oscillating element and feeds the output signal back to the oscillating element. The delay means is (120, 220, 320, 420) tuneable with respect to the delay it provides. The oscillating element can be an amplifier or a VCO, and the delay means can be a Delay Locked Loop or a tuneable delay line, depending on the embodiment of the invention.

    摘要翻译: 本发明公开了一种振荡器电路(100,200,300,400),包括振荡元件(110,210,310,410)和用于从振荡电路输出振荡频率的输出装置(115,215,315,415) 。 电路还包括与振荡元件串联布置的信号延迟装置(120,220,320,420),并将输出信号反馈给振荡元件。 延迟装置是相对于其提供的延迟可调的(120,220,320,420)。 振荡元件可以是放大器或VCO,并且延迟装置可以是延迟锁定环路或可调延迟线路,这取决于本发明的实施例。

    Oscillator circuit with tuneable signal delay means
    5.
    发明授权
    Oscillator circuit with tuneable signal delay means 有权
    具有可调信号延迟装置的振荡电路

    公开(公告)号:US07352253B2

    公开(公告)日:2008-04-01

    申请号:US10581788

    申请日:2003-12-10

    IPC分类号: H03B27/00

    CPC分类号: H03B5/24 H03L7/0812

    摘要: The invention discloses an oscillator circuit (100, 200, 300, 400), comprising an oscillating element (110, 210, 310, 410) and output means (115, 215, 315, 415) for outputting an oscillation frequency from the oscillating circuit. The circuit further comprises a signal delay means (120, 220, 320, 420) which is arranged in series with the oscillating element and feeds the output signal back to the oscillating element. The delay means is (120, 220, 320, 420) tuneable with respect to the delay it provides. The oscillating element can be an amplifier or a VCO, and the delay means can be a Delay Locked Loop or a tuneable delay line, depending on the embodiment of the invention.

    摘要翻译: 本发明公开了一种振荡器电路(100,200,300,400),包括振荡元件(110,210,310,410)和用于从振荡电路输出振荡频率的输出装置(115,215,315,415) 。 电路还包括与振荡元件串联布置的信号延迟装置(120,220,320,420),并将输出信号反馈给振荡元件。 延迟装置是相对于其提供的延迟可调的(120,220,320,420)。 振荡元件可以是放大器或VCO,并且延迟装置可以是延迟锁定环路或可调延迟线路,这取决于本发明的实施例。

    Delay locked loop with precision controlled delay
    6.
    发明授权
    Delay locked loop with precision controlled delay 有权
    具有精确控制延迟的延迟锁定环

    公开(公告)号:US07456664B2

    公开(公告)日:2008-11-25

    申请号:US10581786

    申请日:2003-12-10

    IPC分类号: H03L7/06

    CPC分类号: H03L7/0812

    摘要: The invention discloses a delay-locked loop circuit with input means for a signal that is to be delayed, the input means comprising means for splitting the input signal into a first and a second branch. The signal in the first branch is connected to a component for delaying the signal, and the signal in the second branch is used as a non-delayed reference for the delay caused by the delay component in the first branch. The delay component is a passive tunable delay line, and the circuit comprises tuning means for the tunable delay line, the tuning means being affected by said reference signal, and the first branch comprises output means for outputting a delayed signal with a chosen phase delay. Suitably, the delay component is continuously tunable, for example a tunable ferroelectric delay line.

    摘要翻译: 本发明公开了一种具有用于待延迟的信号的输入装置的延迟锁定环路,输入装置包括用于将输入信号分成第一和第二分支的装置。 第一分支中的信号连接到用于延迟信号的分量,并且第二分支中的信号用作由第一分支中的延迟分量引起的延迟的非延迟参考。 所述延迟部件是无源可调谐延迟线,并且所述电路包括用于所述可调谐延迟线的调谐装置,所述调谐装置受所述参考信号的影响,并且所述第一分支包括用于输出具有所选相位延迟的延迟信号的输出装置。 适当地,延迟分量是可连续调节的,例如可调铁电延迟线。

    Varactor Device with Reduced Temperature Dependence
    7.
    发明申请
    Varactor Device with Reduced Temperature Dependence 有权
    具有降低温度依赖性的变容二极管装置

    公开(公告)号:US20090027132A1

    公开(公告)日:2009-01-29

    申请号:US11577063

    申请日:2004-10-11

    IPC分类号: H03B5/04

    摘要: The invention discloses a varactor device (100) for improved temperature stability, comprising a first varactor (160) connected to a decoupling network (150). The device further comprises a voltage stabilizer (110), said stabilizer comprising a capacitor (140) and a temperature dependent capacitor (130), and in that the stabilizer comprises means for connection to a DC-feed (120). Suitably, the decoupling network (150) is connected in parallel to the first varactor (160), and the capacitor (140) of the voltage stabilizer (110) is connected in parallel to the decoupling network (150), the temperature dependent capacitor (130) of the voltage stabilizer (110) being connected in series to the diode of the voltage stabilizer (110).

    摘要翻译: 本发明公开了一种用于改善温度稳定性的变容二极管装置(100),包括连接到去耦网络(150)的第一变容二极管(160)。 该装置还包括电压稳定器(110),所述稳定器包括电容器(140)和与温度相关的电容器(130),并且所述稳定器包括用于连接到直流馈电(120)的装置。 适当地,解耦网络150并联连接到第一变容二极管160,并且电压稳定器110的电容器140并联连接到去耦网络150,温度依赖电容器 电压稳定器(110)的串联连接到稳压器(110)的二极管。

    Tunable Microwave Arrangements
    8.
    发明申请
    Tunable Microwave Arrangements 有权
    可调谐微波安排

    公开(公告)号:US20070262830A1

    公开(公告)日:2007-11-15

    申请号:US10596687

    申请日:2003-12-30

    IPC分类号: H01P1/203 H01P5/18 H01P7/08

    摘要: The present invention relates to a tunable microwave arrangement (10) comprising a microwave/integrated circuit device (11) and a substrate (6). It comprises a layered structure disposed between said microwave/integrated circuit device and said substrate (5), said layered structure acting as a ground plane and it comprises at least one regularly or irregularly patterned first metal layer (1), at least one second metal layer (3), at least one tunable ferroelectric film layer (2), whereby said layers are so arranged that the ferroelectric film layers) (2) is/are provided between the/a first metal layer (1) and the/a second metal layer (3).

    摘要翻译: 本发明涉及一种包括微波/集成电路器件(11)和衬底(6)的可调谐微波装置(10)。 它包括设置在所述微波/集成电路器件和所述衬底(5)之间的分层结构,所述层状结构用作接地平面,并且其包括至少一个规则或不规则图案化的第一金属层(1),至少一个第二金属 层(3),至少一个可调谐铁电体膜层(2),由此所述层被布置成使得铁电体膜层(2)设置在第一金属层(1)和/或第二金属层 金属层(3)。

    Tunable microwave arrangements
    9.
    发明授权
    Tunable microwave arrangements 有权
    可调微波安排

    公开(公告)号:US07573358B2

    公开(公告)日:2009-08-11

    申请号:US10596687

    申请日:2003-12-30

    IPC分类号: H01P7/08 H01P3/08

    摘要: The present invention relates to a tunable microwave arrangement (10) comprising a microwave/integrated circuit device (11) and a substrate (6). It comprises a layered structure disposed between said microwave/integrated circuit device and said substrate (5), said layered structure acting as a ground plane and it comprises at least one regularly or irregularly patterned first metal layer (1), at least one second metal layer (3), at least one tunable ferroelectric film layer (2), whereby said layers are so arranged that the ferroelectric film layers) (2) is/are provided between the/a first metal layer (1) and the/a second metal layer (3).

    摘要翻译: 本发明涉及一种包括微波/集成电路器件(11)和衬底(6)的可调谐微波装置(10)。 它包括设置在所述微波/集成电路器件和所述衬底(5)之间的分层结构,所述层状结构用作接地平面,并且其包括至少一个规则或不规则图案化的第一金属层(1),至少一个第二金属 层(3),至少一个可调谐铁电体膜层(2),由此所述层被布置成使得铁电体膜层(2)设置在第一金属层(1)和/或第二金属层 金属层(3)。

    Capacitor
    10.
    发明申请
    Capacitor 审中-公开
    电容器

    公开(公告)号:US20070217122A1

    公开(公告)日:2007-09-20

    申请号:US10596664

    申请日:2003-12-23

    IPC分类号: H01G4/232

    摘要: A method of creating a capacitor in an integrated circuit. According to a basic version of the invention the capacitor uses intensive fringing fields to create a capacitance. This is achieved by creating a capacitor with vertical overlapping conducting electrodes between two planes of the integrated circuit, instead of plates parallel to the planes. A capacitor according to the invention can additionally comprise horizontal, i.e. parallel plates. A capacitor according the method is also disclosed.

    摘要翻译: 一种在集成电路中产生电容器的方法。 根据本发明的基本版本,电容器使用密集边缘场来产生电容。 这通过在集成电路的两个平面之间产生具有垂直重叠的导电电极的电容器而不是平行于平面的板来实现。 根据本发明的电容器还可以包括水平的,即平行的板。 还公开了根据该方法的电容器。