公开(公告)号：US20120051147A1

公开(公告)日：2012-03-01

申请号：US12862082

申请日：2010-08-24

Applicant: HSIN-CHANG LIN ,  CHIA-HAO TAI ,  YANG-SEN YEN ,  MING-TSANG YANG ,  YA-TING FAN

Inventor： HSIN-CHANG LIN ,  CHIA-HAO TAI ,  YANG-SEN YEN ,  MING-TSANG YANG ,  YA-TING FAN

IPC: G11C16/04

CPC classification number: G11C16/0416

Abstract: An area saving electrically-erasable-programmable read-only memory (EEPROM) array, having: a plurality of parallel bit lines, a plurality of parallel word lines, and a plurality of parallel common source lines. The bit lines are classified into a plurality of bit line groups, containing a first group bit lines and a second group bit lines; the word line includes a first word line; and the common source lines include a first common source line. In addition, a plurality of sub-memory arrays are provided. Each sub-memory array contains a first, second, third, and fourth memory cells. Wherein, the first and second memory cells are symmetrically arranged, and the third and fourth memory cells are symmetrically arranged; also, the first and second memory cells, and the third and fourth memory cells are symmetrically arranged with the first common source line as a symmetric axis.

Abstract translation: 一种保存电可擦除可编程只读存储器（EEPROM）阵列的区域，其具有：多个并行位线，多个并行字线和多个并行公共源极线。 位线被分成多个位线组，其包含第一组位线和第二组位线; 字线包括第一字线; 并且公共源极线包括第一公共源极线。 另外，提供了多个子存储器阵列。 每个子存储器阵列包含第一，第二，第三和第四存储器单元。 其中，第一和第二存储单元是对称排列的，第三和第四存储单元是对称排列的; 第一和第二存储单元以及第三和第四存储单元也以第一公共源极线为对称轴对称地布置。

公开(公告)号：US20100131535A1

公开(公告)日：2010-05-27

申请号：US12622968

申请日：2009-11-20

Applicant: Hsin-Chang Lin

Inventor： Hsin-Chang Lin

IPC: G06F17/30 ,  G06F3/048

CPC classification number: G06F16/9537 ,  G06F16/29

Abstract: Disclosed is a geographic location identify system with open-type identifier, and further a related method for generating the identifier. One object of the geographic location identify system is to depict information of a spot on a geographic space with open-type identifier that is user-customized with privileged-setting. The system preferably includes a data processing means for processing geographic data by a computer system, and a network connecting means for connecting to plural terminal computers. After a user inputs an open-type geographic location identifier, a means for encoding/decoding is to encode or decode the identifier. A database unit is further included to store the identifier data after encoding. A comparing means is used to compare the identifier data with the input identifier, and a visual presentation generating means is to generate an electronic map, and through the database unit providing the spot related information, based on the user's request.

Abstract translation: 公开了具有开放式标识符的地理位置识别系统，以及用于生成标识符的相关方法。 地理位置识别系统的一个对象是用具有特权设置的用户定制的开放式标识符来描绘地理空间上的点的信息。 该系统优选地包括用于由计算机系统处理地理数据的数据处理装置和用于连接到多个终端计算机的网络连接装置。 在用户输入开放式地理位置标识符之后，用于编码/解码的装置是对标识符进行编码或解码。 还包括数据库单元以在编码之后存储标识符数据。 使用比较装置将标识符数据与输入标识符进行比较，视觉呈现生成装置根据用户的请求，生成电子地图，并通过数据库单元提供相关信息。

公开(公告)号：US20090185429A1

公开(公告)日：2009-07-23

申请号：US12010121

申请日：2008-01-22

Applicant: Hsin Chang Lin ,  Wen Chien Huang ,  Ming Tsang Yang

Inventor： Hsin Chang Lin ,  Wen Chien Huang ,  Ming Tsang Yang

IPC: G11C16/06 ,  H01L29/788

CPC classification number: G11C16/0416 ,  G11C2216/10 ,  H01L27/11558 ,  H01L29/66825 ,  H01L29/788

Abstract: A non-volatile memory with single floating gate and the method for operating the same are proposed. The non-volatile memory is formed by embedding a FET structure in a semiconductor substrate. The FET comprises a single floating gate, a dielectric, and two ion-doped regions in the semiconductor at two sides of the dielectric. The memory cell of the proposed nonvolatile memory with single floating gate can perform many times of operations such as write, erase and read by means of a reverse bias.

Abstract translation: 提出了具有单个浮动栅极的非易失性存储器及其操作方法。 非易失性存储器通过在半导体衬底中嵌入FET结构而形成。 FET包括在电介质的两侧的半导体中的单个浮置栅极，电介质层和两个离子掺杂区域。 所提出的具有单个浮动栅极的非易失性存储器的存储单元可以通过反向偏置执行许多次操作，例如写入，擦除和读取。

公开(公告)号：US07423903B2

公开(公告)日：2008-09-09

申请号：US11403858

申请日：2006-04-14

Applicant: Hsin-Chang Lin ,  Wen-Chien Huang ,  Ming-Tsang Yang ,  Hao-Cheng Chang ,  Cheng-Ying Wu

Inventor： Hsin-Chang Lin ,  Wen-Chien Huang ,  Ming-Tsang Yang ,  Hao-Cheng Chang ,  Cheng-Ying Wu

IPC: G11C14/00

CPC classification number: H01L27/115

Abstract: A single-gate non-volatile memory and an operation method thereof, wherein a transistor and a capacitor structure are embedded in a semiconductor substrate; the transistor comprises: a first electrically-conductive gate, a first dielectric layer, and multiple ion-doped regions; the capacitor structure comprises: a second electrically-conductive gate, a second dielectric layer, and a second on-doped region; the first electrically-conductive gate and the second electrically-conductive gate are interconnected to form a single floating gate of a memory cell; a reverse bias is used to implement the reading, writing, and erasing operations of the single-floating-gate memory cell; in the operation of a single-gate non-volatile memory with an isolation well, positive and negative voltages are applied to the drain, the gate, and the silicon substrate/the isolation well to create an inversion layer so that the absolute voltage, the area of the voltage booster circuit, and the current consumption can be reduced.

Abstract translation: 一种单栅极非易失性存储器及其操作方法，其中晶体管和电容器结构嵌入在半导体衬底中; 所述晶体管包括：第一导电栅极，第一介电层和多个离子掺杂区域; 电容器结构包括：第二导电栅极，第二介电层和第二掺杂区域; 第一导电栅极和第二导电栅极互连以形成存储单元的单个浮置栅极; 使用反向偏置来实现单浮栅存储单元的读，写和擦除操作; 在具有隔离阱的单栅极非易失性存储器的操作中，正和负电压施加到漏极，栅极和硅衬底/隔离阱以产生反型层，使得绝对电压 升压电路的面积，可以减少电流消耗。

公开(公告)号：US20070241392A1

公开(公告)日：2007-10-18

申请号：US11403862

申请日：2006-04-14

Applicant: Hsin-Chang Lin ,  Wen-Chien Huang ,  Ming-Tsang Yang ,  Hao-Cheng Chang ,  Cheng-Ying Wu

Inventor： Hsin-Chang Lin ,  Wen-Chien Huang ,  Ming-Tsang Yang ,  Hao-Cheng Chang ,  Cheng-Ying Wu

IPC: H01L29/788

CPC classification number: H01L29/7881 ,  G11C16/0416 ,  G11C2216/10 ,  H01L27/11521 ,  H01L27/11558 ,  H01L29/66825

Abstract: A non-volatile memory structure and a method for operating the same are proposed. The non-volatile memory structure makes use of a single floating gate structure and a capacitor structure including a pair of regions doped with different type impurities to increase the capacitance and shrink the area. When performing programming operations to this memory structure, a voltage is applied to the source or a back bias is applied to the substrate of the transistor to greatly reduce the current requirement of a single-gate EEPROM device. When performing erase operations, the drain voltage is raised, and a small voltage is added to the gate to increase the F-N tunneling current, thereby accomplishing the effect of fast erase.

Abstract translation: 提出了一种非易失性存储器结构及其操作方法。 非易失性存储器结构使用单个浮置栅极结构和包括掺杂有不同类型杂质的一对区域的电容器结构，以增加电容并缩小面积。 当对该存储器结构执行编程操作时，将电压施加到源极，或者向晶体管的衬底施加反偏压，以大大降低单栅极EEPROM器件的电流需求。 当执行擦除操作时，漏极电压升高，并且向栅极添加小电压以增加F-N隧穿电流，从而实现快速擦除的效果。

公开(公告)号：US05998869A

公开(公告)日：1999-12-07

申请号：US938629

申请日：1997-09-26

Applicant: Hung-Hsueh Lin ,  Hsin-Chang Lin ,  Kow-Liang Wen

Inventor： Hung-Hsueh Lin ,  Hsin-Chang Lin ,  Kow-Liang Wen

IPC: H01L23/50 ,  H01L23/48 ,  H01L23/495 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/06 ,  H01L23/50 ,  H01L24/49 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/48091 ,  H01L2224/49113 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/01058 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14

Abstract: A high storage capacity, wide data channel SRAM having a 64-bit wide data input/output channel, 4 Mbyte or 2 Mbyte of memory, and packaged as a 100-pin QFP or TQFP. The SRAM can be a substitute for a conventional 128 pin QFP or TQFP SRAM because all the functions including pipeline burst transmission are present. Moreover, the SRAM has a comparatively lower package testing and production cost.

Abstract translation: 高存储容量，宽数据通道SRAM，具有64位宽的数据输入/输出通道，4 MB或2 MB的存储器，并封装为100引脚QFP或TQFP。 SRAM可以替代常规的128引脚QFP或TQFP SRAM，因为包括流水线脉冲串传输的所有功能都存在。 此外，SRAM具有相对较低的封装测试和生产成本。