公开(公告)号：US20120040504A1

公开(公告)日：2012-02-16

申请号：US12853450

申请日：2010-08-10

Applicant: HSIN CHANG LIN ,  CHIA-HAO TAI ,  YANG-SEN YEN ,  MING-TSANG YANG ,  YA-TING FAN

Inventor： HSIN CHANG LIN ,  CHIA-HAO TAI ,  YANG-SEN YEN ,  MING-TSANG YANG ,  YA-TING FAN

IPC: H01L21/8246

CPC classification number: H01L27/105 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11526

Abstract: The present invention discloses a method for integrating DRAM and NVM, which comprises steps: sequentially forming on a portion of surface of a DRAM semiconductor substrate a first gate insulation layer and a first gate layer functioning as a floating gate; and implanting ion into regions of the semiconductor substrate, which are at two sides of the first gate insulation layer, to form two heavily-doped areas that are adjacent to the first gate insulation layer and respectively function as a drain and a source; respectively forming over the first gate layer a second gate insulation layer and a second gate layer functioning as a control gate. The present invention not only increases the transmission speed but also reduces the power consumption, the fabrication cost and the package cost.

Abstract translation: 本发明公开了一种用于整合DRAM和NVM的方法，包括以下步骤：在DRAM半导体衬底的表面的一部分上依次形成第一栅极绝缘层和用作浮动栅极的第一栅极层; 以及将离子注入位于所述第一栅极绝缘层两侧的半导体衬底的区域中，以形成与所述第一栅极绝缘层相邻并分别用作漏极和源极的两个重掺杂区域; 分别在第一栅极层上形成第二栅极绝缘层和用作控制栅极的第二栅极层。 本发明不仅提高了传输速度，而且降低了功耗，制造成本和封装成本。

公开(公告)号：US20190201856A1

公开(公告)日：2019-07-04

申请号：US16233578

申请日：2018-12-27

Applicant: CHENG CHI TAI ,  HSIN CHANG LIN ,  CHUN HAO LU

Inventor： CHENG CHI TAI ,  HSIN CHANG LIN ,  CHIA MING HOUNG

IPC: B01F9/00 ,  H02J50/10 ,  B01F9/10 ,  B01F15/00

CPC classification number: B01F9/0001 ,  B01F9/10 ,  B01F15/00538 ,  B01F15/00993 ,  B01F2009/0061 ,  B01F2009/0063 ,  B01F2009/0069 ,  B01F2009/0074 ,  B01F2009/0085 ,  H02J50/10

Abstract: A mixer for mixing and degassing fluids includes a revolution device having a revolution base to be driven for rotation; a first spin device connected to the revolution base of the revolution device; a first barrel connected to the first spin device to be spun by the first spin device; an transmitting coil electrically connected to a power source to generate a time-vary magnetic field; and a receiving coil connected to the revolution base of the revolution device and electrically connected to the first spin device, wherein the receiving coil rotates with the revolution base. The receiving coil receives the power from the time-vary magnetic field of the transmitting coil and produces an electromotive force to be supplied to the first spin device.

公开(公告)号：US08300469B2

公开(公告)日：2012-10-30

申请号：US12854407

申请日：2010-08-11

Applicant: Hsin Chang Lin ,  Chia-Hao Tai ,  Yang-Sen Yen ,  Ming-Tsang Yang ,  Ya-Ting Fan

Inventor： Hsin Chang Lin ,  Chia-Hao Tai ,  Yang-Sen Yen ,  Ming-Tsang Yang ,  Ya-Ting Fan

IPC: G11C16/04

CPC classification number: G11C16/14 ,  G11C16/0441

Abstract: A cost saving EEPROM array, having: a plurality of parallel bit lines, a plurality of parallel word lines, and a plurality of parallel common source lines. The bit lines contain a first group bit lines; the word line includes a first and a second word lines; and the common source line includes a first common source line. And, a plurality of sub-memory arrays are provided. Each sub-memory array includes a first and a second memory cells disposed opposite to each other and located on two different sides of the first common source line; the first memory cell is connected to the first group bit lines, the first common source line, and the first word line, and the second memory cell is connected to the first group bit line, the first common source line, and the second word line.

Abstract translation: 一种节省成本的EEPROM阵列，具有：多个并行位线，多个并行字线和多个并行公共源极线。 位线包含第一组位线; 字线包括第一和第二字线; 并且公共源极线包括第一公共源极线。 并且，提供多个子存储器阵列。 每个子存储器阵列包括彼此相对设置并位于第一公共源极线的两个不同侧上的第​​一和第二存储单元; 第一存储单元连接到第一组位线，第一公共源极线和第一字线，并且第二存储单元连接到第一组位线，第一公共源极线和第二字线 。

公开(公告)号：US08300461B2

公开(公告)日：2012-10-30

申请号：US12862082

申请日：2010-08-24

Applicant: Hsin Chang Lin ,  Chia-Hao Tai ,  Yang-Sen Yen ,  Ming-Tsang Yang ,  Ya-Ting Fan

Inventor： Hsin Chang Lin ,  Chia-Hao Tai ,  Yang-Sen Yen ,  Ming-Tsang Yang ,  Ya-Ting Fan

IPC: G11C11/34

CPC classification number: G11C16/0416

Abstract: An area saving electrically-erasable-programmable read-only memory (EEPROM) array, having: a plurality of parallel bit lines, a plurality of parallel word lines, and a plurality of parallel common source lines. The bit lines are classified into a plurality of bit line groups, containing a first group bit line and a second group bit line; the word line includes a first word line; and the common source lines include a first common source line. In addition, a plurality of sub-memory arrays are provided. Each sub-memory array contains a first, second, third, and fourth memory cells. Wherein, the first and second memory cells are symmetrically arranged, and the third and fourth memory cells are symmetrically arranged; also, the first and second memory cells, and the third and fourth memory cells are symmetrically arranged with the first common source line as a symmetric axis.

Abstract translation: 一种保存电可擦除可编程只读存储器（EEPROM）阵列的区域，其具有：多个并行位线，多个并行字线和多个并行公共源极线。 位线分为多个位线组，包含第一组位线和第二组位线; 字线包括第一字线; 并且公共源极线包括第一公共源极线。 另外，提供了多个子存储器阵列。 每个子存储器阵列包含第一，第二，第三和第四存储器单元。 其中，第一和第二存储单元是对称排列的，第三和第四存储单元是对称排列的; 第一和第二存储单元以及第三和第四存储单元也以第一公共源极线为对称轴对称地布置。

公开(公告)号：US20120039131A1

公开(公告)日：2012-02-16

申请号：US12854989

申请日：2010-08-12

Applicant: HSIN-CHANG LIN ,  CHIA-HAO TAI ,  YANG-SEN YEN ,  MING-TSANG YANG ,  YA-TING FAN

Inventor： HSIN-CHANG LIN ,  CHIA-HAO TAI ,  YANG-SEN YEN ,  MING-TSANG YANG ,  YA-TING FAN

IPC: G11C16/04 ,  H01L29/94

CPC classification number: G11C16/0416 ,  G11C16/0483 ,  G11C16/14 ,  H01L29/7881

Abstract: A low-voltage EEPROM array, which has a plurality of parallel bit lines, parallel word lines and parallel common source lines is disclosed. The bit lines include a first bit line. The word lines include a first word line and a second word line. The common source lines include a first common source line and a second common source line. The low-voltage EEPROM array also has a plurality of sub-memory arrays. Each sub-memory array includes a first memory cell and a second memory cell. The first memory cell connects with the first bit line, the first common source line and the first word line. The second memory cell connects with the first bit line, the second common source line and the second word line. The first and second memory cells are symmetrical and arranged between the first and second common source lines.

Abstract translation: 公开了一种低电压EEPROM阵列，其具有多个并行位线，并行字线和并行公共源极线。 位线包括第一位线。 字线包括第一字线和第二字线。 公共源极线包括第一公共源极线和第二公共源极线。 低电压EEPROM阵列还具有多个子存储器阵列。 每个子存储器阵列包括第一存储单元和第二存储单元。 第一存储单元与第一位线，第一公共源极线和第一字线连接。 第二存储单元与第一位线，第二公共源极线和第二字线连接。 第一和第二存储单元是对称的并且布置在第一和第二公共源极线之间。

公开(公告)号：US20120039129A1

公开(公告)日：2012-02-16

申请号：US12854407

申请日：2010-08-11

Applicant: HSIN CHANG LIN ,  CHIA-HAO TAI ,  YANG-SEN YEN ,  MING-TSANG YANG ,  YA-TING FAN

Inventor： HSIN CHANG LIN ,  CHIA-HAO TAI ,  YANG-SEN YEN ,  MING-TSANG YANG ,  YA-TING FAN

IPC: G11C16/04

CPC classification number: G11C16/14 ,  G11C16/0441

Abstract: A cost saving electrically-erasable-programmable read-only memory (EEPROM) array, having: a plurality of parallel bit lines, a plurality of parallel word lines, and a plurality of parallel common source lines. The bit lines are classified into a plurality of bit line groups, containing a first group bit lines; the word line includes a first and a second word lines; and the common source line includes a first common source line. And, a plurality of sub-memory arrays are provided. Each sub-memory array includes a first and a second memory cells disposed opposite to each other and located on two different sides of the first common source line; the first memory cell is connected to the first group bit lines, the first common source line, and the first word line, and the second memory cell is connected to the first group bit line, the first common source line, and the second word line.

Abstract translation: 一种节省成本的电可擦除可编程只读存储器（EEPROM）阵列，其具有：多个并行位线，多个并行字线和多个并行公共源极线。 位线分为多个位线组，包含第一组位线; 字线包括第一和第二字线; 并且公共源极线包括第一公共源极线。 并且，提供多个子存储器阵列。 每个子存储器阵列包括彼此相对设置并位于第一公共源极线的两个不同侧上的第​​一和第二存储单元; 第一存储单元连接到第一组位线，第一公共源极线和第一字线，并且第二存储单元连接到第一组位线，第一公共源极线和第二字线 。

公开(公告)号：US07508253B1

公开(公告)日：2009-03-24

申请号：US11898384

申请日：2007-09-12

Applicant: Cheng Ying Wu ,  Hsin Chang Lin

Inventor： Cheng Ying Wu ,  Hsin Chang Lin

IPC: G06G7/26 ,  G06G7/12

CPC classification number: H02M3/073 ,  H02M2003/078

Abstract: A charge pump device and an operating method thereof are proposed. The charge pump device is composed of a plurality of stages of charge transfer units and an output unit that are cascaded together. Each stage of the charge transfer units includes a first node for input, a second node for output, a first circuit and a first capacitor. The first node or the second node is biased at a bias provided for the first circuit. Thereby, the first capacitors of the odd-numbered stage and the even-numbered stage of charge transfer units can respectively receive two clock signals that are mutually opposite in phase for complementary switching operating. Collocated with the switching of the output unit, an output voltage with a high negative level can be generated.

Abstract translation: 提出一种电荷泵装置及其操作方法。 电荷泵装置由多级电荷转移单元和串联在一起的输出单元组成。 电荷转移单元的每一级包括用于输入的第一节点，用于输出的第二节点，第一电路和第一电容器。 第一节点或第二节点以为第一电路提供的偏置而偏置。 因此，奇数级的第一电容器和偶数级的电荷转移单元可分别接收相互相反的两个时钟信号，用于互补开关操作。 与输出单元的切换配合，可以产生具有高负电平的输出电压。

公开(公告)号：US20080173915A1

公开(公告)日：2008-07-24

申请号：US12076963

申请日：2008-03-26

Applicant: Hsin-Chang Lin ,  Wen-Chien Huang ,  Ming-Tsang Yang ,  Hao-Cheng Chang ,  Cheng-Ying Wu

Inventor： Hsin-Chang Lin ,  Wen-Chien Huang ,  Ming-Tsang Yang ,  Hao-Cheng Chang ,  Cheng-Ying Wu

IPC: H01L29/94

CPC classification number: H01L27/115

Abstract: A single-gate non-volatile memory and an operation method thereof, wherein a transistor and a capacitor structure are embedded in a semiconductor substrate; the transistor comprises: a first electrically-conductive gate, a first dielectric layer, and multiple ion-doped regions; the capacitor structure comprises: a second electrically-conductive gate, a second dielectric layer, and a second on-doped region; the first electrically-conductive gate and the second electrically-conductive gate are interconnected to form a single floating gate of a memory cell; a reverse bias is used to implement the reading, writing, and erasing operations of the single-floating-gate memory cell; in the operation of a single-gate non-volatile memory with an isolation well, positive and negative voltages are applied to the drain, the gate, and the silicon substrate/the isolation well to create an inversion layer so that the absolute voltage, the area of the voltage booster circuit, and the current consumption can be reduced.

公开(公告)号：US07099192B2

公开(公告)日：2006-08-29

申请号：US10861392

申请日：2004-06-07

Applicant: Lee Zhung Wang ,  Daniel Huang ,  Hsin Chang Lin ,  Roget Chang

Inventor： Lee Zhung Wang ,  Daniel Huang ,  Hsin Chang Lin ,  Roget Chang

IPC: G11C16/04

CPC classification number: G11C16/0416 ,  G11C16/3477 ,  G11C2216/10

Abstract: A nonvolatile memory and a method of operating the same are proposed. The nonvolatile memory has single-gate memory cells, wherein a structure of a transistor and a capacitor is embedded in a semiconductor substrate. The transistor comprises a first conducting gate stacked on the surface of a dielectric with doped regions formed at two sides thereof as a source and a drain. The capacitor comprises a doped region, a dielectric stacked thereon, and a second conducting gate. The conducting gates of the capacitor and the transistor are electrically connected together to form a single floating gate of the memory cell. The semiconductor substrate is p-type or n-type. Besides, a back-bias program write-in and related erase and readout operation ways are proposed for the single-gate memory cells.

Abstract translation: 提出了一种非易失性存储器及其操作方法。 非易失性存储器具有单栅极存储单元，其中晶体管和电容器的结构嵌入在半导体衬底中。 晶体管包括堆叠在电介质的表面上的第一导电栅极，其掺杂区域形成在其两侧作为源极和漏极。 电容器包括掺杂区域，堆叠在其上的电介质和第二导电栅极。 电容器和晶体管的导通栅极电连接在一起以形成存储单元的单个浮置栅极。 半导体衬底是p型或n型。 此外，针对单栅极存储器单元提出了背偏置程序写入和相关的擦除和读出操作方式。

公开(公告)号：US20130181276A1

公开(公告)日：2013-07-18

申请号：US13351319

申请日：2012-01-17

Applicant: HSIN CHANG LIN ,  WEN CHIEN HUANG ,  YA-TING FAN

Inventor： HSIN CHANG LIN ,  WEN CHIEN HUANG ,  YA-TING FAN

IPC: H01L29/788

CPC classification number: H01L29/7881 ,  H01L29/40114 ,  H01L29/42324

Abstract: A non-self aligned non-volatile memory structure includes a semiconductor substrate; a first gate insulation layer on said semiconductor substrate; a floating gate on first gate insulation layer; two doped regions in said semiconductor substrate, which are respectively on two sides of said first gate insulation layer, and adjoining said first gate insulation layer; a second gate insulation layer on said floating gate; and a control gate on said second gate insulation layer. Width of said control gate on said floating gate is less than that of said floating gate, and width of said control gate not on said floating gate is equal to or greater than width of said floating gate. Through the two non-self aligned gates, the non-volatile memory does not need to meet the requirement of gate line-to-line alignment, thus reducing complexity and cost of manufacturing process.

Abstract translation: 非自对准的非易失性存储器结构包括半导体衬底; 在所述半导体衬底上的第一栅极绝缘层; 第一栅绝缘层上的浮栅; 所述半导体衬底中分别位于所述第一栅极绝缘层的两侧上并邻接所述第一栅极绝缘层的两个掺杂区域; 所述浮栅上的第二栅极绝缘层; 以及在所述第二栅极绝缘层上的控制栅极。 所述浮置栅极上的所述控制栅极的宽度小于所述浮动栅极的宽度，而不在所述浮动栅极上的所述控制栅极的宽度等于或大于所述浮动栅极的宽度。 通过两个非自对准门，非易失性存储器不需要满足栅线对线对准的要求，从而降低制造工艺的复杂性和成本。