公开(公告)号：US20080298532A1

公开(公告)日：2008-12-04

申请号：US11757829

申请日：2007-06-04

Applicant: Hui-Min Wang

Inventor： Hui-Min Wang

IPC: H03D3/24

CPC classification number: H03L7/07 ,  H03L7/235 ,  H04N21/4305

Abstract: In an HDMI system, the clock regenerator proposed by the HDMI specification may suffer external noise because the input clock of a phase lock loop circuit in a sink device of the HDMI system is too slow. This slow input clock causes the phase lock loop circuit unable to adjust and reduce the jitter of an audio clock regenerated in the sink device. Therefore, one embodiment of the present invention provides a clock regenerator to extract the relationship between the regenerated audio clock and a video clock received by the sink device from other source devices. The clock regenerator may comprise a phase lock loop circuit, a recovery circuit, a crystal oscillator and a tracking circuit. The crystal oscillator generates a crystal clock. The phase lock loop circuit receives the crystal clock and regenerates an audio clock. The recovery circuit extracts the relationship between the audio clock and the received video clock. The tracking circuit tunes the frequency of the crystal clock based on the extracted relationship.

Abstract translation: 在HDMI系统中，HDMI规范提出的时钟再生器可能会受到外部噪声，因为HDMI系统的信宿设备中的锁相环电路的输入时钟太慢。 这种慢速输入时钟使得锁相环电路不能调节并减少在宿设备中再生的音频时钟的抖动。 因此，本发明的一个实施例提供了一种时钟再生器，用于提取再生的音频时钟与宿设备从其它源设备接收的视频时钟之间的关系。 时钟再生器可以包括锁相环电路，恢复电路，晶体振荡器和跟踪电路。 晶体振荡器产生晶体时钟。 锁相环电路接收晶体钟并重新生成音频时钟。 恢复电路提取音频时钟和接收的视频时钟之间的关系。 跟踪电路根据提取的关系调整晶体时钟的频率。

公开(公告)号：US07446599B1

公开(公告)日：2008-11-04

申请号：US11806107

申请日：2007-05-30

Applicant: Hui-Min Wang

Inventor： Hui-Min Wang

IPC: G05F1/10

CPC classification number: G05F3/242

Abstract: A reference voltage generator is provided. The reference voltage generator includes a bandgap reference circuit, a level shifter and a voltage divider. The bandgap reference circuit includes a current generator and a first BJT. The current generator outputs a reference current. The first BJT flows in the reference current from its emitter via a first resistor and has its collector and base grounded, such that a bandgap reference voltage and a first bias voltage can be output at the connection between the current generator and the first resistor and at the emitter of the first BJT. The level shifter is coupled to the bandgap reference circuit and outputs a second bias voltage higher than the first bias voltage and unequal to the bandgap reference voltage. The voltage divider is connected between the second bias voltage and the bandgap reference voltage and outputs a reference voltage therebetween.

Abstract translation: 提供了参考电压发生器。 参考电压发生器包括带隙参考电路，电平转换器和分压器。 带隙参考电路包括电流发生器和第一BJT。 电流发生器输出参考电流。 第一BJT通过第一电阻器从发射极流过参考电流，并且其集电极和基极接地，使得能够在电流发生器和第一电阻器之间的连接处输出带隙参考电压和第一偏置电压，并且在 第一个BJT的发射器。 电平移位器耦合到带隙参考电路，并输出高于第一偏置电压的第二偏置电压，并且不等于带隙参考电压。 分压器连接在第二偏置电压和带隙参考电压之间，并在其间输出参考电压。

公开(公告)号：US07400174B1

公开(公告)日：2008-07-15

申请号：US11621918

申请日：2007-01-10

Applicant: Hui-Min Wang

Inventor： Hui-Min Wang

IPC: H03K19/0175

CPC classification number: H04L25/0294 ,  H04L25/0282

Abstract: A data communication system comprises a transmitter and a receiver. A plurality of current mode drivers at the transmitter are used to transmit clock and data signals to the receiver. A plurality of current mode sinks at the receiver are used to receive the transmitted clock and data signal. The present invention provides an improved current mode interface receiver with a process insensitive common mode current extraction circuit. The proposed common mode current extraction circuit will generate a current reference based on the received clock signal, so as to accurately interpret the received clock and data signals.

Abstract translation: 数据通信系统包括发射机和接收机。 发射机处的多个电流模式驱动器用于将时钟和数据信号传输到接收机。 在接收机处的多个当前模式信宿用于接收传输的时钟和数据信号。 本发明提供一种具有过程不敏感共模电流提取电路的改进的电流模式接口接收器。 所提出的共模电流提取电路将基于所接收的时钟信号产生电流参考，以便准确地解释所接收的时钟和数据信号。

公开(公告)号：US08455023B2

公开(公告)日：2013-06-04

申请号：US12848380

申请日：2010-08-02

Applicant: Hui-Min Wang ,  Chung-Yi Chen ,  Zhi-Hong Wen

Inventor： Hui-Min Wang ,  Chung-Yi Chen ,  Zhi-Hong Wen

IPC: A61K36/54

CPC classification number: A61K36/54 ,  A61K31/341

Abstract: The present invention provides a Cinnamomum subavenium extract for inhibiting melanogenesis. The present invention also provides a composition for inhibiting melanogenesis including compounds inhibit tyrosinase activity.

Abstract translation: 本发明提供了一种用于抑制黑素生成的樟脑ium ium提取物。 本发明还提供了抑制黑素生成的组合物，包括抑制酪氨酸酶活性的化合物。

公开(公告)号：US20090167366A1

公开(公告)日：2009-07-02

申请号：US11965261

申请日：2007-12-27

Applicant: Hui-Min Wang

Inventor： Hui-Min Wang

IPC: H03B21/00 ,  H03B19/00

CPC classification number: H04N5/775 ,  G09G2370/04 ,  G09G2370/12 ,  H04N5/7755 ,  H04N21/242 ,  H04N21/4302

Abstract: It is difficult to implement a conventional phase lock loop circuit in a sink device within an HDMI system because the low frequency input causes the conventional phase lock loop circuit to absorb unnecessary noise during a long waiting period. Therefore, the present invention provides a low jitter clock regenerator comprises: an input clock; a divider to divide said input clock into a slower clock; a phase lock loop circuit to regenerate said slower clock to a reference clock; and a parameter transformer to tune said divider and said phase lock loop circuit to increase the adjustment speed of said phase lock loop circuit. The present invention also provides a method to reorganize parameters in order to create new parameters which are better suitable for a clock recovery circuit in a sink device within an HDMI system.

Abstract translation: 由于低频输入导致常规锁相环电路在长时间等待期间吸收不必要的噪声，所以难以在HDMI系统内的宿设备中实现传统的锁相环电路。 因此，本发明提供了一种低抖动时钟再生器，包括：输入时钟; 分频器，用于将所述输入时钟分频成较慢的时钟; 用于将所述较慢时钟再生成参考时钟的锁相环电路; 以及参数变压器，用于调谐所述分频器和所述锁相环电路，以增加所述锁相环电路的调节速度。 本发明还提供了一种重组参数以便创建更适合于HDMI系统内的接收器装置中的时钟恢复电路的新参数的方法。

公开(公告)号：US07474245B1

公开(公告)日：2009-01-06

申请号：US11898538

申请日：2007-09-13

Applicant: Hui-Min Wang ,  Chen-Song Yen ,  Chin-Tien Chang ,  Chuan-Che Lee

Inventor： Hui-Min Wang ,  Chen-Song Yen ,  Chin-Tien Chang ,  Chuan-Che Lee

IPC: H03M1/68

CPC classification number: H03M1/682 ,  H03M1/765

Abstract: A digital-to-analog converter outputting an output analog voltage according to an N-bit digital signal is provided. The digital-to-analog converter includes a first and a second resistor strings, a first and a second select units. The first resistor string is connected between a first and a second power supply voltages to generate a first group of reference voltages. The first select unit selects two reference voltages out of the first group according to M most significant bits of the N-bit digital signal. The second resistor string is connected between the selected reference voltages to generate a second group of reference voltages between the selected reference voltages. The second select unit selects one reference voltage out of the second group as the output analog voltage according to the N-M least significant bits of the N-bit digital signal.

Abstract translation: 提供了根据N位数字信号输出输出模拟电压的数模转换器。 数模转换器包括第一和第二电阻串，第一和第二选择单元。 第一电阻串连接在第一和第二电源电压之间以产生第一组参考电压。 第一选择单元根据N位数字信号的M个最高有效位选择第一组中的两个参考电压。 第二电阻串连接在所选择的参考电压之间，以在所选参考电压之间产生第二组参考电压。 第二选择单元根据N位数字信号的N-M个最低有效位选择第二组中的一个参考电压作为输出模拟电压。

公开(公告)号：US20080165898A1

公开(公告)日：2008-07-10

申请号：US11621918

申请日：2007-01-10

Applicant: Hui-Min Wang

Inventor： Hui-Min Wang

IPC: H04L25/06

CPC classification number: H04L25/0294 ,  H04L25/0282

Abstract: A data communication system comprises a transmitter and a receiver. A plurality of current mode drivers at the transmitter are used to transmit clock and data signals to the receiver. A plurality of current mode sinks at the receiver are used to receive the transmitted clock and data signal. The present invention provides an improved current mode interface receiver with a process insensitive common mode current extraction circuit. The proposed common mode current extraction circuit will generate a current reference based on the received clock signal, so as to accurately interpret the received clock and data signals.

Abstract translation: 数据通信系统包括发射机和接收机。 发射机处的多个电流模式驱动器用于将时钟和数据信号传输到接收机。 在接收机处的多个当前模式信宿用于接收传输的时钟和数据信号。 本发明提供一种具有过程不敏感共模电流提取电路的改进的电流模式接口接收器。 所提出的共模电流提取电路将基于所接收的时钟信号产生电流参考，以便准确地解释所接收的时钟和数据信号。

公开(公告)号：US20070222719A1

公开(公告)日：2007-09-27

申请号：US11436226

申请日：2006-05-17

Applicant: Hui-Min Wang ,  Yu-Wen Chiou

Inventor： Hui-Min Wang ,  Yu-Wen Chiou

IPC: G09G3/32

CPC classification number: G09G3/3233 ,  G09G3/3291 ,  G09G2310/0251 ,  G09G2310/061 ,  G09G2320/0233

Abstract: A method pixel driving method of an organic light emitting diode (OLED) display and an apparatus thereof are provided. The method comprises the following steps. First, a pixel unit is reset to a predetermined voltage in a reset time period. After that, a frame period is divided into two driving time periods so that the pixel unit is finally charged to a pixel voltage. The charging process of the pixel unit is that the pixel unit is charged to a ground level in a first driving time period, and then the pixel unit is charged to the pixel voltage in a second driving time period.

Abstract translation: 提供了一种有机发光二极管（OLED）显示器的方法像素驱动方法及其装置。 该方法包括以下步骤。 首先，在复位时间段内将像素单元复位到预定的电压。 之后，将帧周期分为两个驱动时间段，使得像素单元最终被充电到像素电压。 像素单元的充电处理是在第一驱动时间段内将像素单元充电到地电平，然后在第二驱动时间段内将像素单元充电到像素电压。

公开(公告)号：US07014057B2

公开(公告)日：2006-03-21

申请号：US10671053

申请日：2003-09-22

Applicant: Hui-Min Wang

Inventor： Hui-Min Wang

IPC: B65D6/16

CPC classification number: B65D5/3614 ,  B65D2313/02

Abstract: A collapsible container includes a rectangular bottom, a front and a rear rectangular wall pivotally turnably connected to a front and a rear edge, respectively, of the bottom along two folding lines, two rectangular side walls pivotally turnably connected to two lateral ends of each of the front and the rear wall along two folding lines, and two locating flaps pivotally turnably connected to two lateral edges of the bottom along two folding lines. Each of the two locating flaps is an isosceles triangle having two equal lateral sides separately corresponding to a diagonal of the side wall. Moreover, fastening elements are correspondingly provided on an inner surface of each side wall and an outer surface of the locating flap to enable detachable connection of the side walls to the locating flaps and accordingly free collapse and extension of the container.

Abstract translation: 可折叠容器包括矩形底部，前后矩形壁，其分别沿着两条折叠线可转动地连接到底部的前边缘和后边缘，两个矩形侧壁可转动地连接到每个的两个侧端 沿着两条折叠线的前壁和后壁，以及沿两条折叠线可枢转地可转动地连接到底部的两个侧边缘的两个定位翼片。 两个定位翼片中的​​每一个是具有分别对应于侧壁的对角线的两个相等侧边的等腰三角形。 此外，紧固元件相应地设置在每个侧壁的内表面和定位翼片的外表面上，以使得侧壁能够与定位翼片可拆卸地连接，并因此自由地使容器的塌缩和延伸。

公开(公告)号：US06281819B1

公开(公告)日：2001-08-28

申请号：US09541859

申请日：2000-04-03

Applicant: Wen-Ching Wu ,  Hui-Min Wang

Inventor： Wen-Ching Wu ,  Hui-Min Wang

IPC: H03M110

CPC classification number: H03M1/1095 ,  H03M1/12

Abstract: Disclosed are a device and method therefor for ENOB (effective number of bits) estimation for an ADC (analog-to-digital converter) based on dynamic deviation, wherein the correlation between dynamic deviation and ENOB is analyzed so as to provide a novel device and method therefor to estimate and calculate ENOB for an ADC. Dynamic deviation, provided in the present invention, can serve as a novel parameter for use in evaluation of the performance of an ADC. The present invention further provides a model related to the relation of distribution of dynamic deviation and input frequency, wherein ENOB can be therefore predicted for higher input frequency for an ADC without a high-quality signal generator by measuring dynamic deviation for lower input frequency.

Abstract translation: 公开了一种用于基于动态偏差的ADC（模拟 - 数字转换器）的ENOB（有效位数）估计的装置和方法，其中分析动态偏差与ENOB之间的相关性，以便提供新颖的装置和 用于估计和计算ADC的ENOB的方法。 在本发明中提供的动态偏差可以用作用于评估ADC性能的新颖参数。 本发明还提供了与动态偏差和输入频率分布的关系相关的模型，其中可以通过测量较低输入频率的动态偏差来为没有高质量信号发生器的ADC预测用于较高输入频率的ENOB。