公开(公告)号：US20080148021A1

公开(公告)日：2008-06-19

申请号：US12036704

申请日：2008-02-25

申请人： Jonathan James DeMent ,  Kurt Alan Feiste ,  Robert Alan Philhower ,  David Shippy

发明人： Jonathan James DeMent ,  Kurt Alan Feiste ,  Robert Alan Philhower ,  David Shippy

IPC分类号： G06F9/312

CPC分类号： G06F9/3836 ,  G06F9/3838 ,  G06F9/3875

摘要： An issue unit includes a first instruction stage, a second instruction stage, and issue control logic. During a first instruction cycle, the issue unit performs two tasks, which are 1) the instructions located in the first instruction stage are moved to a second instruction stage, and 2) the issue control logic determines whether to issue or stall the instructions that are moved to the second instruction stage based upon their particular instruction attributes and the issue control unit's previous state. During a second instruction cycle that immediately follows the first instruction cycle, the second instruction stage's instructions are either issued or stalled based upon the issue control logic's decision from the first instruction cycle.

摘要翻译： 发行单元包括第一指令阶段，第二指令阶段和发布控制逻辑。 在第一指令周期期间，发行单元执行两个任务，即1）位于第一指令阶段的指令移动到第二指令阶段，2）发行控制逻辑确定是否发出或停止指令 基于其特定的指令属性和发布控制单元的先前状态，移动到第二指令阶段。 在紧随第一指令周期的第二指令周期中，基于从第一指令周期的发布控制逻辑的判定，发出或停止第二指令级的指令。

公开(公告)号：US20070083742A1

公开(公告)日：2007-04-12

申请号：US11246587

申请日：2005-10-07

申请人： Christopher Michael Abernathy ,  Jonathan James DeMent ,  Ronald Hall ,  Robert Philhower ,  David Shippy

发明人： Christopher Michael Abernathy ,  Jonathan James DeMent ,  Ronald Hall ,  Robert Philhower ,  David Shippy

IPC分类号： G06F7/38

CPC分类号： G06F9/3836 ,  G06F9/3838 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/3861

摘要： A system and method for tracking the order of issued instructions using a counter is presented. In one embodiment, a saturating, decrementing counter is used. The counter is initialized to a value that corresponds to the processor's commit point. Instructions are issued from a first issue queue to one or more execution units and one or more second issue queues. After being issued by the first issue queue, the counter associated with each instruction is decremented during each instruction cycle until the instruction is executed by one of the execution units. Once the counter reaches zero it will be completed by the execution unit. If a flush condition occurs, instructions with counters equal to zero are maintained (i.e., not flushed or invalidated), while other instructions in the pipeline are invalidated based upon their counter values.

摘要翻译： 提出了一种用于跟踪使用计数器发出的指令顺序的系统和方法。 在一个实施例中，使用饱和的递减计数器。 计数器初始化为与处理器提交点对应的值。 指令从第一个问题队列发送到一个或多个执行单元和一个或多个第二个问题队列。 在通过第一个发出队列发出后，与每个指令相关联的计数器在每个指令周期中递减，直到指令由其中一个执行单元执行。 一旦计数器达到零，将由执行单元完成。 如果发生冲洗状况，则保持具有等于零的计数器的指令（即，不刷新或无效），而管道中的其他指令基于其计数器值而无效。

公开(公告)号：US20090077352A1

公开(公告)日：2009-03-19

申请号：US12277376

申请日：2008-11-25

申请人： Christopher Michael Abernathy ,  Jonathan James Dement ,  Ronald Hall ,  Albert James Van Norstrand

发明人： Christopher Michael Abernathy ,  Jonathan James Dement ,  Ronald Hall ,  Albert James Van Norstrand

IPC分类号： G06F9/38

CPC分类号： G06F9/3836 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863

摘要： A method, system and processor for improving the performance of an in-order processor. A processor may include an execution unit with an execution pipeline that includes a backup pipeline and a regular pipeline. The backup pipeline may store a copy of the instructions issued to the regular pipeline. The execution pipeline may include logic for allowing instructions to flow from the backup pipeline to the regular pipeline following the flushing of the instructions younger than the exception detected in the regular pipeline. By maintaining a backup copy of the instructions issued to the regular pipeline, instructions may not need to be flushed from separate execution pipelines and re-fetched. As a result, one may complete the results of the execution units to the architected state out of order thereby allowing the completion point to vary among the different execution pipelines.

摘要翻译： 一种用于改善按顺序处理器的性能的方法，系统和处理器。 处理器可以包括具有包括备用流水线和常规流水线的执行流水线的执行单元。 备用管道可以存储发给正常管道的指令的副本。 执行流水线可以包括逻辑，用于在刷新比正常流水线中检测到的异常之后的指令更新时允许指令从备用流水线流向正常流水线。 通过维护发布到常规流水线的指令的备份副本，可能不需要从单独的执行流程中刷新指令并重新获取。 结果，可以将执行单元的结果完成到设计状态，从而使完成点在不同执行流水线之间变化。

公开(公告)号：US20090043997A1

公开(公告)日：2009-02-12

申请号：US12250285

申请日：2008-10-13

申请人： Christopher Michael Abernathy ,  Jonathan James DeMent ,  Ronald Hall ,  Robert Alan Philhower ,  David Shippy

发明人： Christopher Michael Abernathy ,  Jonathan James DeMent ,  Ronald Hall ,  Robert Alan Philhower ,  David Shippy

IPC分类号： G06F7/38

CPC分类号： G06F9/3836 ,  G06F9/3838 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/3861

摘要： Tracking the order of issued instructions using a counter is presented. In one embodiment, a saturating, decrementing counter is used. The counter is initialized to a value that corresponds to the processor's commit point. Instructions are issued from a first issue queue to one or more execution units and one or more second issue queues. After being issued by the first issue queue, the counter associated with each instruction is decremented during each instruction cycle until the instruction is executed by one of the execution units. Once the counter reaches zero it will be completed by the execution unit. If a flush condition occurs, instructions with counters equal to zero are maintained (i.e., not flushed or invalidated), while other instructions in the pipeline are invalidated based upon their counter values.

摘要翻译： 介绍使用计数器跟踪发出的指令的顺序。 在一个实施例中，使用饱和的递减计数器。 计数器初始化为与处理器提交点对应的值。 指令从第一个问题队列发送到一个或多个执行单元和一个或多个第二个问题队列。 在通过第一个发出队列发出后，与每个指令相关联的计数器在每个指令周期中递减，直到指令由其中一个执行单元执行。 一旦计数器达到零，将由执行单元完成。 如果发生冲洗状况，则保持具有等于零的计数器的指令（即，不刷新或无效），而管道中的其他指令基于其计数器值而无效。

公开(公告)号：US20090019255A1

公开(公告)日：2009-01-15

申请号：US11777319

申请日：2007-07-13

申请人： Adam Patrick Burns ,  Jason Nathaniel Dale ,  Jonathan James DeMent ,  Gavin Balfour Meil

发明人： Adam Patrick Burns ,  Jason Nathaniel Dale ,  Jonathan James DeMent ,  Gavin Balfour Meil

IPC分类号： G06F12/10

CPC分类号： G06F12/126

摘要： A system, method, and program product are provided that identifies a cache set using Segment LookAside Buffer attributes. When an effective address is requested, an attempt is made to load the received effective address from an L2 cache. When this attempt results in a cache miss, the system identifies a segment within the Segment LookAside Buffer that includes the effective address. A class identifier is retrieved from the identified segment within the Segment LookAside Buffer. This class identifier identifies a cache set selected from the cache for replacement. Data is then reloaded into the cache set of the cache by using the retrieved class identifier that corresponds to the effective address.

摘要翻译： 提供了使用Segment LookAside Buffer属性标识高速缓存集的系统，方法和程序产品。 当请求有效地址时，尝试从L2高速缓存加载接收到的有效地址。 当此尝试导致高速缓存未命中时，系统会识别段内LookAside缓冲区中包含有效地址的段。 从Segment LookAside缓冲区中的标识段检索类标识符。 该类标识符标识从高速缓存中选择的用于替换的高速缓存集。 然后通过使用与有效地址对应的检索到的类标识符将数据重新加载到高速缓存的高速缓存集中。

公开(公告)号：US07475232B2

公开(公告)日：2009-01-06

申请号：US11184349

申请日：2005-07-19

申请人： Christopher Michael Abernathy ,  Jonathan James Dement ,  Ronald Hall ,  Albert James Van Norstrand

发明人： Christopher Michael Abernathy ,  Jonathan James Dement ,  Ronald Hall ,  Albert James Van Norstrand

IPC分类号： G06F9/00

CPC分类号： G06F9/3836 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863

摘要： A method, system and processor for improving the performance of an in-order processor. A processor may include an execution unit with an execution pipeline that includes a backup pipeline and a regular pipeline. The backup pipeline may store a copy of the instructions issued to the regular pipeline. The execution pipeline may include logic for allowing instructions to flow from the backup pipeline to the regular pipeline following the flushing of the instructions younger than the exception detected in the regular pipeline. By maintaining a backup copy of the instructions issued to the regular pipeline, instructions may not need to be flushed from separate execution pipelines and re-fetched. As a result, one may complete the results of the execution units to the architected state out of order thereby allowing the completion point to vary among the different execution pipelines.

摘要翻译： 一种用于改善按顺序处理器的性能的方法，系统和处理器。 处理器可以包括具有包括备用流水线和常规流水线的执行流水线的执行单元。 备用管道可以存储发给正常管道的指令的副本。 执行流水线可以包括逻辑，用于在刷新比正常流水线中检测到的异常之后的指令更新时允许指令从备用流水线流向正常流水线。 通过维护发布到常规流水线的指令的备份副本，可能不需要从单独的执行流程中刷新指令并重新获取。 结果，可以将执行单元的结果完成到设计状态，从而使完成点在不同执行流水线之间变化。

公开(公告)号：US20080229078A1

公开(公告)日：2008-09-18

申请号：US12130736

申请日：2008-05-30

申请人： Christopher Michael Abernathy ,  Jonathan James DeMent ,  Ronald Hall ,  Robert Alan Philhower ,  David Shippy

发明人： Christopher Michael Abernathy ,  Jonathan James DeMent ,  Ronald Hall ,  Robert Alan Philhower ,  David Shippy

IPC分类号： G06F9/30

CPC分类号： G06F1/3237 ,  G06F1/3228 ,  G06F1/3243 ,  G06F9/3867 ,  Y02D10/128 ,  Y02D10/152

摘要： Dynamic power management in a processor design is presented. A pipeline stage's stall detection logic detects a stall condition, and sends a signal to idle detection logic to gate off the pipeline's register clocks. The stall detection logic also monitors a downstream pipeline stage's stall condition, and instructs the idle detection logic to gate off the pipeline stage's registers when the downstream pipeline stage is in a stall condition as well. In addition, when the pipeline stage's stall detection logic detects a stall condition, either from the downstream pipeline stage or from its own pipeline units, the pipeline stage's stall detection logic informs an upstream pipeline stage to gate off its clocks and thus, conserve more power.

摘要翻译： 介绍了处理器设计中的动态电源管理。 流水线阶段的失速检测逻辑检测失速状态，并将信号发送到空闲检测逻辑以关闭流水线的寄存器时钟。 失速检测逻辑还监视下游流水线阶段的失速状态，并且当下游流水线阶段处于失速状态时，指示空闲检测逻辑关闭流水线级的寄存器。 此外，当流水线级的失速检测逻辑检测到停顿条件时，无论是从下游流水线级还是从其自身的管道单元，流水线级的失速检测逻辑通知上游流水线级别关闭其时钟，从而节省更多的功率 。

公开(公告)号：US07350056B2

公开(公告)日：2008-03-25

申请号：US11236838

申请日：2005-09-27

申请人： Christopher Michael Abernathy ,  Jonathan James DeMent ,  Kurt Alan Feiste ,  David Shippy

发明人： Christopher Michael Abernathy ,  Jonathan James DeMent ,  Kurt Alan Feiste ,  David Shippy

IPC分类号： G06F9/30

CPC分类号： G06F9/3836 ,  G06F9/3814 ,  G06F9/3838 ,  G06F9/3855

摘要： An information handling system includes a processor that issues instructions out of program order. The processor includes an issue queue that may advance instructions toward issue even though some instructions in the queue are not ready-to-issue. The issue queue includes a matrix of storage cells configured in rows and columns including a first row that couples to execution units. Instructions advance toward issuance from row to row as unoccupied storage cells appear. Unoccupied cells appear when instructions advance toward the first row and upon issuance. When a particular row includes an instruction that is not ready-to-issue a stall condition occurs for that instruction. However, to prevent the entire issue queue and processor from stalling, a ready-to-issue instruction in another row may bypass the row including the stalled or not-ready-to-issue instruction. Out-of-order issuance of instructions to the execution units thus continues.

摘要翻译： 信息处理系统包括处理器，其以程序顺序发出指令。 处理器包括一个问题队列，即使队列中的某些指令还没有准备就绪，也可能提前发出指令。 问题队列包括以行和列配置的存储单元矩阵，包括耦合到执行单元的第一行。 显示从空行到无存储单元格时，逐行发行的说明。 当指示向第一行发出时，出现未占用的单元格。 当特定行包含一个尚未准备就绪的指令时，该指令发生停顿状态。 然而，为了防止整个问题队列和处理器停止，另一行中的就绪指令可能绕过包括已停止或尚未就绪的指令的行。 因此，对执行单元的指令的无序发布继续进行。

公开(公告)号：US07328330B2

公开(公告)日：2008-02-05

申请号：US11204413

申请日：2005-08-16

申请人： Christopher Michael Abernathy ,  Jonathan James DeMent ,  Ronald Hall ,  David Shippy

发明人： Christopher Michael Abernathy ,  Jonathan James DeMent ,  Ronald Hall ,  David Shippy

IPC分类号： G06F9/30 ,  G06F9/40 ,  G06F15/00

CPC分类号： G06F9/3836 ,  G06F9/3838 ,  G06F9/3859 ,  G06F9/3885 ,  G06F9/3887

摘要： A method, an apparatus and a computer program product are provided for the managing of SIMD instructions and GP instructions within an instruction pipeline of a processor. The SIMD instructions and the GP instructions share the same “front-end” pipelines within an Instruction Unit. Within the shared pipelines the Instruction Unit checks the GP instructions for dependencies and resolves these dependencies. At the dispatch point within the pipelines the Instruction Unit sends valid GP instructions to the GP Unit and SIMD instructions to an SIMD issue queue. In the SIMD issue queue the Instruction Unit checks the SIMD instructions for dependencies and resolves these dependencies. Then the SIMD issue queue dispatches the SIMD instructions to the SIMD Unit. Accordingly, dependencies involving SIMD instructions do not affect GP instructions because the SIMD dependencies are checked and resolved independently.

摘要翻译： 提供了一种用于管理处理器的指令流水线内的SIMD指令和GP指令的方法，装置和计算机程序产品。 SIMD指令和GP指令在指令单元内共享相同的“前端”管道。 在共享管道中，指令单元检查GP指令的依赖关系并解决这些依赖关系。 在管线内的调度点，指令单元向GP单元发送有效的GP指令，向SIMD发出队列发送SIMD指令。 在SIMD问题队列中，指令单元检查SIMD指令的依赖性并解决这些依赖关系。 然后SIMD问题队列将SIMD指令发送到SIMD单元。 因此，涉及SIMD指令的依赖关系不会影响GP指令，因为SIMD依赖性被独立地检查和解决。

公开(公告)号：US20070288776A1

公开(公告)日：2007-12-13

申请号：US11423291

申请日：2006-06-09

申请人： Jonathan James DeMent ,  Clark McKerall O'Niell ,  Steven Leonard Roberts

发明人： Jonathan James DeMent ,  Clark McKerall O'Niell ,  Steven Leonard Roberts

IPC分类号： G06F1/32

CPC分类号： G06F1/3275 ,  G06F1/3225 ,  Y02D10/13 ,  Y02D10/14

摘要： A computer implemented method, apparatus, and computer usable program code for managing power consumption in a cache. A set of sections is identified in the cache used by the process in response to identifying a process requesting access to a cache. Power is enabled to each section in the set of sections in which power is disabled. The power is disabled to sections outside of the set of sections in which power is enabled.

摘要翻译： 一种用于管理高速缓存中的功耗的计算机实现的方法，装置和计算机可用程序代码。 响应于识别请求访问高速缓存的进程，在进程使用的缓存中识别出一组部分。 电源被禁用的部分中的每个部分启用了电源。 电源被禁用在启用电源的部分组之外的部分。