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公开(公告)号：US07370176B2
公开(公告)日：2008-05-06
申请号：US11204414
申请日：2005-08-16
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/3875
摘要： A system and method for a high frequency stall design is presented. An issue unit includes a first instruction stage, a second instruction stage, and issue control logic. During a first instruction cycle, the issue unit performs two tasks, which are 1) the instructions located in the first instruction stage are moved to a second instruction stage, and 2) the issue control logic determines whether to issue or stall the instructions that are moved to the second instruction stage based upon their particular instruction attributes and the issue control unit's previous state. During a second instruction cycle that immediately follows the first instruction cycle, the second instruction stage's instructions are either issued or stalled based upon the issue control logic's decision from the first instruction cycle.
摘要翻译： 提出了一种用于高频失速设计的系统和方法。 发行单元包括第一指令阶段，第二指令阶段和发布控制逻辑。 在第一指令周期期间，发行单元执行两个任务，即1）位于第一指令阶段的指令移动到第二指令阶段，2）发行控制逻辑确定是否发出或停止指令 基于其特定的指令属性和发布控制单元的先前状态，移动到第二指令阶段。 在紧随第一指令周期的第二指令周期中，基于从第一指令周期的发布控制逻辑的判定，发出或停止第二指令级的指令。
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公开(公告)号：US20080148021A1
公开(公告)日：2008-06-19
申请号：US12036704
申请日：2008-02-25
IPC分类号： G06F9/312
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/3875
摘要： An issue unit includes a first instruction stage, a second instruction stage, and issue control logic. During a first instruction cycle, the issue unit performs two tasks, which are 1) the instructions located in the first instruction stage are moved to a second instruction stage, and 2) the issue control logic determines whether to issue or stall the instructions that are moved to the second instruction stage based upon their particular instruction attributes and the issue control unit's previous state. During a second instruction cycle that immediately follows the first instruction cycle, the second instruction stage's instructions are either issued or stalled based upon the issue control logic's decision from the first instruction cycle.
摘要翻译： 发行单元包括第一指令阶段，第二指令阶段和发布控制逻辑。 在第一指令周期期间，发行单元执行两个任务，即1）位于第一指令阶段的指令移动到第二指令阶段，2）发行控制逻辑确定是否发出或停止指令 基于其特定的指令属性和发布控制单元的先前状态，移动到第二指令阶段。 在紧随第一指令周期的第二指令周期中，基于从第一指令周期的发布控制逻辑的判定，发出或停止第二指令级的指令。
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3.发明授权Method and apparatus for issuing instructions from an issue queue in an information handling system 失效用于从信息处理系统中的发布队列发出指令的方法和装置公开(公告)号：US07350056B2
公开(公告)日：2008-03-25
申请号：US11236838
申请日：2005-09-27
IPC分类号： G06F9/30
CPC分类号： G06F9/3836 , G06F9/3814 , G06F9/3838 , G06F9/3855
摘要： An information handling system includes a processor that issues instructions out of program order. The processor includes an issue queue that may advance instructions toward issue even though some instructions in the queue are not ready-to-issue. The issue queue includes a matrix of storage cells configured in rows and columns including a first row that couples to execution units. Instructions advance toward issuance from row to row as unoccupied storage cells appear. Unoccupied cells appear when instructions advance toward the first row and upon issuance. When a particular row includes an instruction that is not ready-to-issue a stall condition occurs for that instruction. However, to prevent the entire issue queue and processor from stalling, a ready-to-issue instruction in another row may bypass the row including the stalled or not-ready-to-issue instruction. Out-of-order issuance of instructions to the execution units thus continues.
摘要翻译： 信息处理系统包括处理器，其以程序顺序发出指令。 处理器包括一个问题队列，即使队列中的某些指令还没有准备就绪，也可能提前发出指令。 问题队列包括以行和列配置的存储单元矩阵，包括耦合到执行单元的第一行。 显示从空行到无存储单元格时，逐行发行的说明。 当指示向第一行发出时，出现未占用的单元格。 当特定行包含一个尚未准备就绪的指令时，该指令发生停顿状态。 然而，为了防止整个问题队列和处理器停止，另一行中的就绪指令可能绕过包括已停止或尚未就绪的指令的行。 因此，对执行单元的指令的无序发布继续进行。
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公开(公告)号：US07681056B2
公开(公告)日：2010-03-16
申请号：US12130736
申请日：2008-05-30
申请人： Christopher Michael Abernathy , Jonathan James DeMent , Ronald Hall , Robert Alan Philhower , David Shippy
发明人： Christopher Michael Abernathy , Jonathan James DeMent , Ronald Hall , Robert Alan Philhower , David Shippy
CPC分类号： G06F1/3237 , G06F1/3228 , G06F1/3243 , G06F9/3867 , Y02D10/128 , Y02D10/152
摘要： Dynamic power management in a processor design is presented. A pipeline stage's stall detection logic detects a stall condition, and sends a signal to idle detection logic to gate off the pipeline's register clocks. The stall detection logic also monitors a downstream pipeline stage's stall condition, and instructs the idle detection logic to gate off the pipeline stage's registers when the downstream pipeline stage is in a stall condition as well. In addition, when the pipeline stage's stall detection logic detects a stall condition, either from the downstream pipeline stage or from its own pipeline units, the pipeline stage's stall detection logic informs an upstream pipeline stage to gate off its clocks and thus, conserve more power.
摘要翻译： 介绍了处理器设计中的动态电源管理。 流水线阶段的失速检测逻辑检测失速状态，并将信号发送到空闲检测逻辑以关闭流水线的寄存器时钟。 失速检测逻辑还监视下游流水线阶段的失速状态，并且当下游流水线阶段处于失速状态时，指示空闲检测逻辑关闭流水线级的寄存器。 此外，当流水线级的失速检测逻辑检测到停顿条件时，无论是从下游流水线级还是从其自身的管道单元，流水线级的失速检测逻辑通知上游流水线级别关闭其时钟，从而节省更多的功率 。
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公开(公告)号：US07913070B2
公开(公告)日：2011-03-22
申请号：US12250285
申请日：2008-10-13
申请人： Christopher Michael Abernathy , Jonathan James DeMent , Ronald Hall , Robert Alan Philhower , David Shippy
发明人： Christopher Michael Abernathy , Jonathan James DeMent , Ronald Hall , Robert Alan Philhower , David Shippy
IPC分类号： G06F7/38
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/3855 , G06F9/3857 , G06F9/3859 , G06F9/3861
摘要： Tracking the order of issued instructions using a counter is presented. In one embodiment, a saturating, decrementing counter is used. The counter is initialized to a value that corresponds to the processor's commit point. Instructions are issued from a first issue queue to one or more execution units and one or more second issue queues. After being issued by the first issue queue, the counter associated with each instruction is decremented during each instruction cycle until the instruction is executed by one of the execution units. Once the counter reaches zero it will be completed by the execution unit. If a flush condition occurs, instructions with counters equal to zero are maintained (i.e., not flushed or invalidated), while other instructions in the pipeline are invalidated based upon their counter values.
摘要翻译： 介绍使用计数器跟踪发出的指令的顺序。 在一个实施例中，使用饱和的递减计数器。 计数器初始化为与处理器提交点对应的值。 指令从第一个问题队列发送到一个或多个执行单元和一个或多个第二个问题队列。 在通过第一个发出队列发出后，与每个指令相关联的计数器在每个指令周期中递减，直到指令由其中一个执行单元执行。 一旦计数器达到零，将由执行单元完成。 如果发生冲洗状况，则保持具有等于零的计数器的指令（即，不刷新或无效），而管道中的其他指令基于其计数器值而无效。
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6.发明授权公开(公告)号：US07490224B2
公开(公告)日：2009-02-10
申请号：US11246587
申请日：2005-10-07
申请人： Christopher Michael Abernathy , Jonathan James DeMent , Ronald Hall , Robert Alan Philhower , David Shippy
发明人： Christopher Michael Abernathy , Jonathan James DeMent , Ronald Hall , Robert Alan Philhower , David Shippy
IPC分类号： G06F9/30
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/3855 , G06F9/3857 , G06F9/3859 , G06F9/3861
摘要： Tracking the order of issued instructions using a counter is presented. In one embodiment, a saturating, decrementing counter is used. The counter is initialized to a value that corresponds to the processor's commit point. Instructions are issued from a first issue queue to one or more execution units and one or more second issue queues. After being issued by the first issue queue, the counter associated with each instruction is decremented during each instruction cycle until the instruction is executed by one of the execution units. Once the counter reaches zero it will be completed by the execution unit. If a flush condition occurs, instructions with counters equal to zero are maintained (i.e., not flushed or invalidated), while other instructions in the pipeline are invalidated based upon their counter values.
摘要翻译： 介绍使用计数器跟踪发出的指令的顺序。 在一个实施例中，使用饱和的递减计数器。 计数器初始化为与处理器提交点对应的值。 指令从第一个问题队列发送到一个或多个执行单元和一个或多个第二个问题队列。 在通过第一个发出队列发出后，与每个指令相关联的计数器在每个指令周期中递减，直到指令由其中一个执行单元执行。 一旦计数器达到零，将由执行单元完成。 如果发生冲洗状况，则保持具有等于零的计数器的指令（即，不刷新或无效），而管道中的其他指令基于其计数器值而无效。
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公开(公告)号：US07401242B2
公开(公告)日：2008-07-15
申请号：US11236657
申请日：2005-09-27
申请人： Christopher Michael Abernathy , Jonathan James DeMent , Ronald Hall , Robert Alan Philhower , David Shippy
发明人： Christopher Michael Abernathy , Jonathan James DeMent , Ronald Hall , Robert Alan Philhower , David Shippy
CPC分类号： G06F1/3237 , G06F1/3228 , G06F1/3243 , G06F9/3867 , Y02D10/128 , Y02D10/152
摘要： A pipeline stage's stall detection logic detects a stall condition, and sends a signal to idle detection logic to gate off the pipeline's register clocks. The stall detection logic also monitors a downstream pipeline stage's stall condition, and instructs the idle detection logic to gate off the pipeline stage's registers when the downstream pipeline stage is in a stall condition as well. In addition, when the pipeline stage's stall detection logic detects a stall condition, either from the downstream pipeline stage or from its own pipeline units, the pipeline stage's stall detection logic informs an upstream pipeline stage to gate off its clocks and thus, conserve more power.
摘要翻译： 流水线阶段的失速检测逻辑检测失速状态，并将信号发送到空闲检测逻辑以关闭流水线的寄存器时钟。 失速检测逻辑还监视下游流水线阶段的失速状态，并且当下游流水线阶段处于失速状态时，指示空闲检测逻辑关闭流水线级的寄存器。 此外，当流水线级的失速检测逻辑检测到停顿条件时，无论是从下游流水线级还是从其自身的管道单元，流水线级的失速检测逻辑通知上游流水线级别关闭其时钟，从而节省更多的功率 。
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公开(公告)号：US20090043997A1
公开(公告)日：2009-02-12
申请号：US12250285
申请日：2008-10-13
申请人： Christopher Michael Abernathy , Jonathan James DeMent , Ronald Hall , Robert Alan Philhower , David Shippy
发明人： Christopher Michael Abernathy , Jonathan James DeMent , Ronald Hall , Robert Alan Philhower , David Shippy
IPC分类号： G06F7/38
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/3855 , G06F9/3857 , G06F9/3859 , G06F9/3861
摘要： Tracking the order of issued instructions using a counter is presented. In one embodiment, a saturating, decrementing counter is used. The counter is initialized to a value that corresponds to the processor's commit point. Instructions are issued from a first issue queue to one or more execution units and one or more second issue queues. After being issued by the first issue queue, the counter associated with each instruction is decremented during each instruction cycle until the instruction is executed by one of the execution units. Once the counter reaches zero it will be completed by the execution unit. If a flush condition occurs, instructions with counters equal to zero are maintained (i.e., not flushed or invalidated), while other instructions in the pipeline are invalidated based upon their counter values.
摘要翻译： 介绍使用计数器跟踪发出的指令的顺序。 在一个实施例中，使用饱和的递减计数器。 计数器初始化为与处理器提交点对应的值。 指令从第一个问题队列发送到一个或多个执行单元和一个或多个第二个问题队列。 在通过第一个发出队列发出后，与每个指令相关联的计数器在每个指令周期中递减，直到指令由其中一个执行单元执行。 一旦计数器达到零，将由执行单元完成。 如果发生冲洗状况，则保持具有等于零的计数器的指令（即，不刷新或无效），而管道中的其他指令基于其计数器值而无效。
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公开(公告)号：US20080229078A1
公开(公告)日：2008-09-18
申请号：US12130736
申请日：2008-05-30
申请人： Christopher Michael Abernathy , Jonathan James DeMent , Ronald Hall , Robert Alan Philhower , David Shippy
发明人： Christopher Michael Abernathy , Jonathan James DeMent , Ronald Hall , Robert Alan Philhower , David Shippy
IPC分类号： G06F9/30
CPC分类号： G06F1/3237 , G06F1/3228 , G06F1/3243 , G06F9/3867 , Y02D10/128 , Y02D10/152
摘要： Dynamic power management in a processor design is presented. A pipeline stage's stall detection logic detects a stall condition, and sends a signal to idle detection logic to gate off the pipeline's register clocks. The stall detection logic also monitors a downstream pipeline stage's stall condition, and instructs the idle detection logic to gate off the pipeline stage's registers when the downstream pipeline stage is in a stall condition as well. In addition, when the pipeline stage's stall detection logic detects a stall condition, either from the downstream pipeline stage or from its own pipeline units, the pipeline stage's stall detection logic informs an upstream pipeline stage to gate off its clocks and thus, conserve more power.
摘要翻译： 介绍了处理器设计中的动态电源管理。 流水线阶段的失速检测逻辑检测失速状态，并将信号发送到空闲检测逻辑以关闭流水线的寄存器时钟。 失速检测逻辑还监视下游流水线阶段的失速状态，并且当下游流水线阶段处于失速状态时，指示空闲检测逻辑关闭流水线级的寄存器。 此外，当流水线级的失速检测逻辑检测到停顿条件时，无论是从下游流水线级还是从其自身的管道单元，流水线级的失速检测逻辑通知上游流水线级别关闭其时钟，从而节省更多的功率 。
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10.发明申请QUEUE DESIGN SYSTEM SUPPORTING DEPENDENCY CHECKING AND ISSUE FOR SIMD INSTRUCTIONS WITHIN A GENERAL PURPOSE PROCESSOR 有权QUEUE设计系统支持在一般用途处理器中的SIMD指令的依赖性检查和问题公开(公告)号：US20080168261A1
公开(公告)日：2008-07-10
申请号：US11961914
申请日：2007-12-20
IPC分类号： G06F9/30
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/3859 , G06F9/3885 , G06F9/3887
摘要： A processor includes a general purpose (GP) unit adapted to receive and configured to execute GP instructions; and includes a single instruction multiple data (SIMD) unit adapted to receive and configured to execute SIMD instructions. An instruction unit comprises a first logic unit coupled to the GP unit and a second logic unit coupled to the SIMD unit, wherein SIMD instructions are processed subsequent to GP instructions. In the first logic unit a GP instruction with unresolved dependencies unconditionally causes subsequent SIMD instructions to stall, and an SIMD instruction with unresolved dependencies does not cause subsequent GP instructions to stall. The first logic unit resolves dependencies in GP instructions, provides dependency-free instructions to the GP unit, and provides SIMD instructions to the second logic unit. The second logic unit resolves dependencies in SIMD instructions and provides dependency-free instructions to the SIMD unit.
摘要翻译： 处理器包括适于接收和配置为执行GP指令的通用（GP）单元; 并且包括适于接收和配置为执行SIMD指令的单指令多数据（SIMD）单元。 指令单元包括耦合到GP单元的第一逻辑单元和耦合到SIMD单元的第二逻辑单元，其中在GP指令之后处理SIMD指令。 在第一个逻辑单元中，具有未解决的依赖关系的GP指令无条件地导致后续的SIMD指令停止，并且具有未解决依赖性的SIMD指令不会导致后续的GP指令停止。 第一个逻辑单元解决GP指令中的依赖关系，向GP单元提供无依赖指令，并向第二个逻辑单元提供SIMD指令。 第二个逻辑单元解决SIMD指令中的依赖关系，并向SIMD单元提供无依赖指令。
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