摘要:
In a crystal growth method, a seed crystal 8 and a source material 4 are provided in spaced relation inside of a growth crucible 6. Starting conditions for the growth of a crystal 14 in the growth crucible 6 are then established therein. The starting conditions include: a suitable gas inside the growth crucible 6, a suitable pressure of the gas inside the growth crucible 6, and a suitable temperature in the growth crucible 6 that causes the source material 4 to sublimate and be transported via a temperature gradient in the growth crucible 6 to the seed crystal 8 where the sublimated source material precipitates. During growth of the crystal 14 inside the growth crucible 6, at least one of the following growth conditions are intermittently changed inside the growth crucible 6 a plurality of times: the gas in the growth crucible 6, the pressure of the gas in the growth crucible 6, and the temperature in the growth crucible 6.
摘要:
A method of preparing a silicon melt in a crucible for use in the manufacture of cast silicon, wherein the crucible comprises an opening, an opposing bottom surface, and at least one sidewall joining the opening and the bottom surface. The method comprises charging a silicon spacer to the bottom surface of the crucible; arranging a monocrystalline silicon seed crystal on the silicon spacer such that no surface of the monocrystalline silicon material is in contact with the bottom surface of the crucible; charging polycrystalline silicon feedstock to the crucible; and applying heat through at least one of the opening and the at least one sidewall in order to form a partially melted charge of silicon in the crucible.
摘要:
A method of forming an associated transistor is presented whereby short channel effects and junction capacitances are mitigated and enhanced switching speeds are thereby facilitated. Compensation regions are formed within a substrate by implanting dopants relatively deeply over source and drain regions formed within the substrate. The compensation regions are spaced apart slightly less than are the source and drain regions. This spacing affects potential contours and reduces junction capacitances within the transistor. The different distances between the source and drain regions and the compensation regions are achieved by forming and selectively adjusting sidewall spacers adjacent to a gate structure of the transistor. These spacers serve as guides for the dopants implanted into the substrate to form the source and drain regions and the compensation regions.