公开(公告)号：US07767022B1

公开(公告)日：2010-08-03

申请号：US11788384

申请日：2007-04-19

申请人： Avinash K. Gupta ,  Ilya Zwieback ,  Jihong Chen ,  Marcus Getkin ,  Walter R. M. Stepko ,  Edward Semenas

发明人： Avinash K. Gupta ,  Ilya Zwieback ,  Jihong Chen ,  Marcus Getkin ,  Walter R. M. Stepko ,  Edward Semenas

IPC分类号： C30B23/00

CPC分类号： C30B29/36 ,  C30B23/00 ,  C30B33/02

摘要： A crystal is sublimation grown in a crucible by way of a temperature gradient in the presence of between 1 and 200 Torr of inert gas. The pressure of the inert gas is then increased to between 300 and 600 Torr, while the temperature gradient is maintained substantially constant. The temperature gradient is then reduced and the temperature in the crucible is increased sufficiently to anneal the crystal. Following cooling and removal from the crucible, the crystal is heated in the presence of oxygen in an enclosure to a temperature sufficient to remove unwanted material from the crystal. Following cooling and removal from the enclosure, the crystal surrounded by another instance of the source material is heated in a crucible in the presence 200 and 600 Torr of inert gas to a temperature sufficient to anneal the crystal.

摘要翻译： 在惰性气体的1至200乇的存在下，通过温度梯度在坩埚中生长晶体。 然后将惰性气体的压力增加到300至600托之间，同时温度梯度保持基本恒定。 然后降低温度梯度，并使坩埚中的温度充分增加以使晶体退火。 在从坩埚中冷却和除去之后，将晶体在外壳中的氧气存在下加热到足以从晶体去除不需要的材料的温度。 在从壳体冷却和除去之后，将源材料的另一个实例包围的晶体在惰性气体存在的200和600乇的坩埚中加热到足以使晶体退火的温度。

公开(公告)号：US20090220788A1

公开(公告)日：2009-09-03

申请号：US12096306

申请日：2006-12-07

申请人： Donovan L. Barrett ,  Jihong Chen ,  Richard H. Hopkins ,  Carl J. Johnson

发明人： Donovan L. Barrett ,  Jihong Chen ,  Richard H. Hopkins ,  Carl J. Johnson

IPC分类号： C01B31/36 ,  B32B5/16

CPC分类号： C04B35/573 ,  C01B32/956 ,  C04B2235/422 ,  C04B2235/428 ,  C04B2235/6562 ,  C04B2235/6565 ,  C04B2235/6584 ,  Y10T428/2982

摘要： Adsorbed gaseous species and elements in a carbon (C) powder and a graphite crucible are reduced by way of a vacuum and an elevated temperature sufficient to cause reduction. A wall and at least one end of an interior of the crucible is lined with C powder purified in the above manner. An Si+C mixture is formed with C powder purified in the above manner and Si powder or granules. The lined crucible is charged with the Si+C mixture. Adsorbed gaseous species and elements are reduced from the Si+C mixture and the crucible by way of a vacuum and an elevated temperature that is sufficient to cause reduction but which does not exceed the melting point of Si. Thereafter, by way of a vacuum and an elevated temperature, the Si+C mixture is caused to react and form polycrystalline SiC.

摘要翻译： 吸附的气态物质和碳（C）粉末和石墨坩埚中的元素通过真空和足以引起还原的升高的温度被还原。 坩埚内壁的壁和至少一端用上述方式纯化的C粉末排列。 用上述方法纯化的C粉末和Si粉末或颗粒形成Si + C混合物。 衬里的坩埚中加入Si + C混合物。 吸附的气态物质和元素通过真空和升高的温度从Si + C混合物和坩埚中还原，足以引起还原但不超过Si的熔点。 此后，通过真空和升高的温度，使Si + C混合物反应并形成多晶SiC。

公开(公告)号：US20080190355A1

公开(公告)日：2008-08-14

申请号：US11629584

申请日：2005-07-06

申请人： Jihong Chen ,  Ilya Zwieback ,  Avinash K. Gupta ,  Donovan L. Barrett ,  Richard H. Hopkins ,  Edward Semenas ,  Thomas A. Anderson ,  Andrew E. Souzis

发明人： Jihong Chen ,  Ilya Zwieback ,  Avinash K. Gupta ,  Donovan L. Barrett ,  Richard H. Hopkins ,  Edward Semenas ,  Thomas A. Anderson ,  Andrew E. Souzis

IPC分类号： C30B33/02 ,  H01B1/02

CPC分类号： H01L29/1608 ,  C30B23/00 ,  C30B29/36 ,  H01L21/02378 ,  H01L21/02529 ,  H01L21/02581 ,  H01L21/02631

摘要： The invention relates to substrates of semi-insulating silicon carbide used for semiconductor devices and a method for making the same. The substrates have a resistivity above 106 Ohm-cm, and preferably above 108 Ohm-cm, and most preferably above 109 Ohm-cm, and a capacitance below 5 pF/mm2 and preferably below 1 pF/mm2. The electrical properties of the substrates are controlled by a small amount of added deep level impurity, large enough in concentration to dominate the electrical behavior, but small enough to avoid structural defects. The substrates have concentrations of unintentional background impurities, including shallow donors and acceptors, purposely reduced to below 5·1016 cm−3, and preferably to below 1·1016 cm−3, and the concentration of deep level impurity is higher, and preferably at least two times higher, than the difference between the concentrations of shallow acceptors and shallow donors. The deep level impurity comprises one of selected metals from the periodic groups IB, IIB, IIIB, IVB, VB, VIB, VIIB and VIIIB. Vanadium is a preferred deep level element. In addition to controlling the resistivity and capacitance, a further advantage of the invention is an increase in electrical uniformity over the entire crystal and reduction in the density of crystal defects.

摘要翻译： 本发明涉及用于半导体器件的半绝缘碳化硅的衬底及其制造方法。 基板的电阻率高于106欧姆 - 厘米，优选高于108欧姆 - 厘米，最优选高于109欧姆 - 厘米，电容低于5 pF / mm2，最好低于1 pF / mm2。 基板的电学特性由少量的加入的深度杂质控制，其浓度足够大以控制电气行为，但足够小以避免结构缺陷。 底物具有无意的背景杂质浓度，包括浅供体和受体，故意降低至5.1016cm-3以下，优选低于1.1016cm-3，深层杂质的浓度较高，优选至少高两倍 ，比浅受体和浅供体的浓度之间的差异。 深层杂质包括选自周期性基团IB，IIB，IIIB，IVB，VB，VIB，VIIB和VIIIB的金属之一。 钒是首选的深层元素。 除了控制电阻率和电容之外，本发明的另一个优点是在整个晶体上的电均匀性的增加和晶体缺陷密度的降低。

公开(公告)号：US20050263897A1

公开(公告)日：2005-12-01

申请号：US11182929

申请日：2005-07-15

申请人： Kaiping Liu ,  Zhiqiang Wu ,  Jihong Chen

发明人： Kaiping Liu ,  Zhiqiang Wu ,  Jihong Chen

IPC分类号： H01L21/00 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/44 ,  H01L21/461 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L29/49

CPC分类号： H01L21/28035 ,  H01L29/4916

摘要： A method of forming a semiconductor device includes implanting a precipitate into a gate conductor of an at least partially formed semiconductor device. The gate conductor including a plurality of semiconductor grains. The boundaries of adjacent grains forming a dopant migration path. A plurality of precipitate regions are formed within the gate conductor. At least some of the precipitate regions located at a junction of at least two grains. The gate conductor of the at least partially formed semiconductor device is doped with a dopant. The dopant diffuses inwardly along the dopant migration path.

公开(公告)号：US6060372A

公开(公告)日：2000-05-09

申请号：US823286

申请日：1997-03-21

申请人： Michael C. Smayling ,  Alister C. Young ,  John A. Rodriguez ,  Jihong Chen

发明人： Michael C. Smayling ,  Alister C. Young ,  John A. Rodriguez ,  Jihong Chen

IPC分类号： H01L21/28 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/822 ,  H01L21/265

CPC分类号： H01L21/28123 ,  H01L21/76216 ,  H01L21/823481

摘要： A semiconductor device (10) of the present invention has a gate (32) insulatively disposed above the substrate, source and drain regions (36, 38) disposed near the surface in the substrate adjacent opposite sides of the gate (32), and a field oxide region (26) disposed in the surface of the substrate surrounding the source and drain regions (36, 38) and defining an active moat region (20). The channel stop region (24) is disposed below the field oxide region (26) and is spaced from the active moat region (20) with a predetermined spacing.

摘要翻译： 本发明的半导体器件（10）具有绝缘地设置在衬底之上的栅极（32），源极和漏极区域（36,38）设置在邻近栅极（32）的相对侧的衬底中的表面附近，以及 设置在围绕源极和漏极区域（36,38）的基板的表面中并且限定活动的护城河区域（20）的场氧化物区域（26）。 通道停止区域（24）设置在场氧化物区域（26）的下方，并且以预定的间隔与活动的护壕区域（20）间隔开。

公开(公告)号：US20130193559A1

公开(公告)日：2013-08-01

申请号：US13360144

申请日：2012-01-27

申请人： Jihong Chen

发明人： Jihong Chen

IPC分类号： H01L29/30

CPC分类号： H01L31/028 ,  C30B11/002 ,  C30B11/14 ,  H01L31/03682 ,  H01L31/182 ,  Y02E10/546 ,  Y02E10/547 ,  Y02P70/521

摘要： A cast silicon crystalline ingot comprises two major generally parallel surfaces, one of which is the front surface and the other of which is the back surface; a perimeter surface connecting the front surface and the back surface; and a bulk region between the front surface and the back surface; wherein the cast silicon crystalline ingot has no transverse dimension less than about five centimeters; the cast silicon crystalline ingot has a dislocation density of less than 1000 dislocations/cm2. Wafers sliced from the cast silicon crystalline ingot have solar cell efficiency of at least 17.5% and light induced degradation no greater than 0.2%.

摘要翻译： 铸造硅晶锭包括两个主要的大致平行的表面，其中一个是前表面，另一个是后表面; 连接前表面和后表面的周边表面; 以及前表面和后表面之间的主体区域; 其中所述铸造硅晶锭的横向尺寸不小于约5厘米; 铸硅晶锭的位错密度小于1000位错/ cm2。 从铸硅晶锭切片的晶片具有至少17.5％的太阳能电池效率和光诱导的降解不大于0.2％。

公开(公告)号：US07371648B2

公开(公告)日：2008-05-13

申请号：US11469512

申请日：2006-09-01

申请人： Jihong Chen ,  Srinivasan Chakravarthi ,  Eddie H. Breashears ,  Amitabh Jain

发明人： Jihong Chen ,  Srinivasan Chakravarthi ,  Eddie H. Breashears ,  Amitabh Jain

IPC分类号： H01L21/336 ,  H01L21/04 ,  H01L21/425

CPC分类号： H01L29/7833 ,  H01L21/26506 ,  H01L21/823814 ,  H01L29/6656 ,  H01L29/6659

摘要： The present invention provides a method for manufacturing a transistor device, and a method for manufacturing an integrated circuit including the same. The method for manufacturing the transistor device, among other elements, includes forming a gate structure over a substrate, implanting an atom selected from the group consisting of fluorine, silicon, or germanium into the substrate proximate the gate structure to cause at least a portion of the substrate to be in a sub-amorphous state, and implanting a dopant into the substrate having the implanted atom therein, thereby forming source/drain regions in the substrate, wherein the transistor device does not have a halo/pocket implant.

摘要翻译： 本发明提供一种晶体管器件的制造方法及其制造方法。 制造晶体管器件的方法以及其它元件包括在衬底上形成栅极结构，将选自氟，硅或锗的原子在栅极结构附近植入到衬底中，以使至少一部分 所述衬底处于亚非晶态，并且将掺杂剂注入到其中具有注入原子的衬底中，从而在衬底中形成源极/漏极区，其中所述晶体管器件不具有卤素/穴袋注入。

公开(公告)号：US20080057654A1

公开(公告)日：2008-03-06

申请号：US11469512

申请日：2006-09-01

申请人： Jihong Chen ,  Srinivasan Chakravarthi ,  Eddie H. Breashears ,  Amitabh Jain

发明人： Jihong Chen ,  Srinivasan Chakravarthi ,  Eddie H. Breashears ,  Amitabh Jain

IPC分类号： H01L21/336

CPC分类号： H01L29/7833 ,  H01L21/26506 ,  H01L21/823814 ,  H01L29/6656 ,  H01L29/6659

摘要： The present invention provides a method for manufacturing a transistor device, and a method for manufacturing an integrated circuit including the same. The method for manufacturing the transistor device, among other elements, includes forming a gate structure over a substrate, implanting an atom selected from the group consisting of fluorine, silicon, or germanium into the substrate proximate the gate structure to cause at least a portion of the substrate to be in a sub-amorphous state, and implanting a dopant into the substrate having the implanted atom therein, thereby forming source/drain regions in the substrate, wherein the transistor device does not have a halo/pocket implant.

摘要翻译： 本发明提供一种晶体管器件的制造方法及其制造方法。 制造晶体管器件的方法以及其它元件包括在衬底上形成栅极结构，将选自氟，硅或锗的原子在栅极结构附近植入到衬底中，以使至少一部分 所述衬底处于亚非晶态，并且将掺杂剂注入到其中具有注入原子的衬底中，从而在衬底中形成源极/漏极区，其中所述晶体管器件不具有卤素/穴袋注入。

公开(公告)号：US20070283418A1

公开(公告)日：2007-12-06

申请号：US11344894

申请日：2006-02-01

申请人： Jihong Chen ,  Sam Hsu ,  Saeed Rajput

发明人： Jihong Chen ,  Sam Hsu ,  Saeed Rajput

IPC分类号： G06F7/04

CPC分类号： G06F21/31

摘要： A system for authenticating access to a data processing device or database is provided. The system includes a comparison module for comparing an attempt identifier with an account identifier, and a state-determining module for determining a state variable associated with at least one of the attempt identifier and the account identifier. The state-determining module determines the state variable by incrementing the state variable if the attempt identifier does not match the account identifier and if the state variable is less than a predetermined upper bound threshold, decrementing the state variable if the attempt identifier does match the account identifier and if the state variable is greater than a predetermined lower bound threshold, and authenticating the attempt identifier if the attempt identifier does match the account identifier and if the state variable equals the predetermined lower bound threshold.

摘要翻译： 提供了用于认证对数据处理设备或数据库的访问的系统。 该系统包括用于将尝试标识符与帐户标识符进行比较的比较模块，以及用于确定与至少一个尝试标识符和帐户标识符相关联的状态变量的状态确定模块。 状态确定模块如果尝试标识符与帐户标识符不匹配并且如果状态变量小于预定的上限阈值则通过递增状态变量来确定状态变量，如果尝试标识符与帐户匹配则递减状态变量 标识符，如果状态变量大于预定的下限阈值，并且如果尝试标识符与帐户标识符匹配并且状态变量等于预定下限阈值则认证尝试标识符。

公开(公告)号：US20070278557A1

公开(公告)日：2007-12-06

申请号：US11443779

申请日：2006-05-31

申请人： Jihong Chen ,  Eddie Hearl Breashears ,  Xin Wang ,  John Howard Macpeak

发明人： Jihong Chen ,  Eddie Hearl Breashears ,  Xin Wang ,  John Howard Macpeak

IPC分类号： H01L29/788

CPC分类号： H01L29/7881 ,  H01L21/26586 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/40114

摘要： An embedded memory device and method of forming MOS transistors having reduced masking requirements and defects using a single drain sided halo implant in the NMOS FLASH or EEPROM memory regions is discussed. The memory device comprises a memory region and a logic region. Logic transistors within the logic region have halos implanted at an angle underlying the channel from both drain and source region sides. Asymmetric memory cell transistors within the memory region receive a selective halo implant only from the drain side of the channel and not from the source side to form a larger halo on the drain side and leave a higher dopant concentration more deeply into the source side. One method of asymmetrically forming memory cell transistors comprises masking over the memory region; halo implanting a first conductivity dopant in NMOS regions of the logic region in first and second implant directions; masking over the logic region; halo implanting the first conductivity dopant in NMOS regions of the memory region in the second implant direction only, thereby reducing the number of masks required; masking over the memory region; halo implanting a second conductivity dopant in PMOS regions of the logic region in the first and second implant directions.

摘要翻译： 讨论了在NMOS闪存或EEPROM存储器区域中使用单个漏极侧卤素注入形成具有减小的掩模要求和缺陷的MOS晶体管的嵌入式存储器件和方法。 存储器件包括存储器区域和逻辑区域。 逻辑区域内的逻辑晶体管具有从沟道和源极区两侧的通道下方的角度注入的光晕。 存储器区域内的不对称存储单元晶体管仅从沟道的漏极侧接收选择性晕圈注入而不从源极接收，以在漏极侧形成较大的卤素，并且在源极侧更高的掺杂浓度。 一种不对称形成存储单元晶体管的方法包括：对存储区进行掩蔽; 在第一和第二植入方向上在所述逻辑区域的NMOS区域中注入第一电导率掺杂剂; 屏蔽逻辑区域; 在第二注入方向仅在存储区域的NMOS区域中注入第一电导率掺杂剂，从而减少所需的掩模数量; 掩蔽内存区域; 在所述第一和第二植入方向上在所述逻辑区域的PMOS区域中注入第二电导率掺杂剂。