公开(公告)号：US5017813A

公开(公告)日：1991-05-21

申请号：US522389

申请日：1990-05-11

申请人： Douglas C. Galbraith ,  Jonathan W. Greene

发明人： Douglas C. Galbraith ,  Jonathan W. Greene

IPC分类号： G06F3/00 ,  H03K19/0175

CPC分类号： H03K19/017581 ,  H03K19/01759

摘要： An input/output module circuit for providing input/output interface functions in integrated circuits includes an input section and an output section electrically connected to an I/O pad of the integrated circuit. The input section includes an input buffer/level shifter for translating the logic signals from the outside world to CMOS compatible levels. The input buffer may be placed in a high impedance state by a control signal applied to a control input. The output of the input buffer/level shifter is connected to a first data input of a two-input multiplexer. The output of the two-input multiplexer is connected to an internal bus and to the second data input of the two-input multiplexer. The select input of the two-input multiplexer is connected to a control signal, preferably to the same control signal used to enable the input buffer/level shifter. The output section of the input/output module section of the present invention includes a two-input multiplexer having a first input connected to an internal data bus, and its output fed back to its second data input. Its select input is driven from a control signal. The output of the two-input multiplexer is also connected to the input of an HCT buffer. The output of the HCT buffer is connected to an I/O pad of the integrated circuit, which may be the same pad to which the input section is connected. The slew input of the HCT buffer is driven from a signal enabling slow or fast rise times. The enable input of the HCT buffer is driven from an enable signal which may be derived from other logic signals.

公开(公告)号：US07932744B1

公开(公告)日：2011-04-26

申请号：US12142118

申请日：2008-06-19

申请人： Jonathan W. Greene ,  Gregory W. Bakker ,  Suhail Zain

发明人： Jonathan W. Greene ,  Gregory W. Bakker ,  Suhail Zain

IPC分类号： H03K19/177

CPC分类号： H03K19/17744 ,  H01L24/06 ,  H01L2224/05554 ,  H01L2924/14 ,  H01L2924/00

摘要： An I/O scheme for an integrated circuit includes a group layout cell. The group layout cell includes a plurality of signal I/O pads. A driver circuit is coupled to each signal I/O pad. The group layout cell also includes two I/O driver-circuit power-supply pads. ESD protection circuitry is coupled to the plurality of driver circuits. The signal I/O pads and the I/O driver-circuit power-supply pads are arranged in rows. The rows may be regular or staggered.

摘要翻译： 集成电路的I / O方案包括组布局单元。 组布局单元包括多个信号I / O焊盘。 驱动器电路耦合到每个信号I / O焊盘。 组布局单元还包括两个I / O驱动器电路电源板。 ESD保护电路耦合到多个驱动器电路。 信号I / O焊盘和I / O驱动器电路电源板排列成行。 行可以是规则的或交错的。

公开(公告)号：US07919977B2

公开(公告)日：2011-04-05

申请号：US12860004

申请日：2010-08-20

申请人： Jonathan W. Greene ,  John McCollum ,  Volker Hecht

发明人： Jonathan W. Greene ,  John McCollum ,  Volker Hecht

IPC分类号： H03K19/00 ,  H01L25/00

CPC分类号： H03K19/17764 ,  G01R31/318519 ,  H03K19/17736

摘要： An FPGA architecture includes multiplexers having non-volatile switches having control gates coupled to word lines W, each word line associated with a row, the switches connecting to wiring tracks through buffers having a controllable ground connection NGND, at least some of the switches being a tie-off switch coupleable to one of a plurality of bitlines B, each bitline associated with column.

摘要翻译： FPGA架构包括具有非易失性开关的多路复用器，其具有耦合到字线W的控制栅极，与行相关联的每个字线，所述开关通过具有可控接地连接NGND的缓冲器连接到布线轨道，至少一些开关是 连接开关可耦合到多个位线B中的一个，每个位线与列相关联。

公开(公告)号：US5440245A

公开(公告)日：1995-08-08

申请号：US028789

申请日：1993-03-09

申请人： Douglas C. Galbraith ,  Abbas El Gamal ,  Jonathan W. Greene

发明人： Douglas C. Galbraith ,  Abbas El Gamal ,  Jonathan W. Greene

IPC分类号： H03K3/037 ,  H03K19/173 ,  H03K19/177

CPC分类号： H03K19/1737 ,  H03K3/037

摘要： A logic module includes a first and a second two-input multiplexer each having first and second data inputs. Both the first and second multiplexer include a select input, both of which are connected to the output of a two-input logic gate of a first type having first and second data inputs. The inputs to the first and second two-input multiplexers are sourced with data signals from a first group. One input of each of the logic gates is sourced from a data signal of a second group and the other input of each of the logic gates is sourced from a data signal of a third group. A third two-input multiplexer has its first and second data inputs connected the outputs of the first and second multiplexers, respectively. A select input of the third two-input multiplexer is connected to the output of a two input logic gate of a second type having first and second data inputs. The output of the third two-input multiplexer is connected to a first data input of a fourth two-input multiplexer having a HOLD1 input coupled to its select input. Its output is and a CLEAR input are presented to an AND gate whose output is connected to the second data input of the fourth two-input multiplexer and to the first data input of a fifth two-input multiplexer. The select input of the fifth two-input multiplexer is connected to a HOLD2 input. Its output and the CLEAR input are presented to an AND gate whose output is connected to the second data input of the fifth two-input multiplexer and to an output node. The CLEAR, HOLD1 and HOLD2 inputs are defined by combinations of signals from a data signal of a third group which may contain a data signal of one of the other groups.

摘要翻译： 逻辑模块包括第一和第二双输入多路复用器，每个具有第一和第二数据输入。 第一和第二多路复用器都包括选择输入，它们都连接到具有第一和第二数据输入的具有第一类型的双输入逻辑门的输出。 对第一和​​第二双输入多路复用器的输入来自第一组的数据信号。 每个逻辑门的一个输入源自第二组的数据信号，并且每个逻辑门的另一个输入源自第三组的数据信号。 第三双输入多路复用器具有分别连接第一和第二多路复用器的输出的第一和第二数据输入。 第三双输入多路复用器的选择输入连接到具有第一和第二数据输入的具有第二类型的两输入逻辑门的输出。 第三双输入多路复用器的输出连接到具有耦合到其选择输入的HOLD1输入的第四双输入多路复用器的第一数据输入。 其输出为CLEAR输入，并将其输出连接到第四个双输入多路复用器的第二数据输入端和第五个双输入多路复用器的第一个数据输入端的与门。 第五个双输入多路复用器的选择输入连接到一个HOLD2输入。 其输出和CLEAR输入被呈现给AND门，其输出端连接到第五个双输入多路复用器的第二个数据输入端和一个输出节点。 CLEAR，HOLD1和HOLD2输入由来自第三组的数据信号的组合组成，其可以包含其他组中的一个的数据信号。