公开(公告)号：US5665991A

公开(公告)日：1997-09-09

申请号：US456238

申请日：1995-05-31

Applicant: Taylor R. Efland ,  Satwinder Malhi ,  Michael C. Smayling ,  Joseph A. Devore ,  Ross E. Teggatz ,  Alec J. Morton

Inventor： Taylor R. Efland ,  Satwinder Malhi ,  Michael C. Smayling ,  Joseph A. Devore ,  Ross E. Teggatz ,  Alec J. Morton

IPC: H01L23/482 ,  H01L23/528 ,  H01L29/417 ,  H01L29/78 ,  H01L23/522

CPC classification number: H01L23/5286 ,  H01L23/4824 ,  H01L29/41725 ,  H01L29/41758 ,  H01L29/7816 ,  H01L29/7835 ,  H01L2924/0002

Abstract: The device has a semiconductor chip having active circuitry in the face thereof. The circuitry has busing over it containing two conductive layers having a plurality of contacts and vias with spacings between them that alternate with respect to one another to provide current ballasting and improved switching uniformity. The spacings between the alternating contacts and vias provide regions of maximum conductor thickness and therefore reduces the busing resistance. Staggering the rows of alternating contacts and vias provides further current ballasting. A first conducting layer is used to contact and provide electrically isolated low resistive conducting paths to the various semiconductor regions while the second conducting region is used to provide selective contact to the first conductive layer, thus providing a means of busing large currents over active semiconductor area without sacrificing performance parameters.

Abstract translation: 该器件具有在其表面上具有有源电路的半导体芯片。 该电路具有引线，其中包含两个具有多个触点的导电层和在它们之间具有相互间交替的间隙的通孔，以提供电流镇流和改善的开关均匀性。 交替触点和通孔之间的间距提供最大导体厚度的区域，因此降低了阻抗。 交错的交替触点和通孔的排列提供了进一步的电流镇流。 第一导电层用于接触并提供到各种半导体区域的电隔离的低电阻导电路径，而第二导电区域用于提供与第一导电层的选择性接触，从而提供在有源半导体区域上引入大电流的装置 而不牺牲性能参数。

公开(公告)号：US06324044B1

公开(公告)日：2001-11-27

申请号：US09305571

申请日：1999-05-05

Applicant: Ross E. Teggatz ,  Joseph A. Devore ,  Timothy J. Legat ,  Timothy P. Pauletti ,  David J. Baldwin

Inventor： Ross E. Teggatz ,  Joseph A. Devore ,  Timothy J. Legat ,  Timothy P. Pauletti ,  David J. Baldwin

IPC: H02H100

CPC classification number: G06F13/385

Abstract: A controlled area network (CAN) driver provides improved symmetry between its differential output signals CAN-H and CAN-L, and provides protection for its low voltage devices from voltage transients occurring on its output lines. A plurality of CAN drivers 80 are serially interconnected to form a driver system, wherein each downstream driver stage receives a time-delayed form of the digital input signal TxD, each stage providing a time-delayed contribution to the differential output signals of the overall driver system.

Abstract translation: 控制区域网络（CAN）驱动器在其差分输出信号CAN-H和CAN-L之间提供改进的对称性，并为其低压器件提供对其输出线路上发生的电压瞬变的保护。 多个CAN驱动器80串联互连以形成驱动器系统，其中每个下游驱动器级接收时间延迟形式的数字输入信号TxD，每个级为整个驱动器的差分输出信号提供时间延迟的贡献 系统。

公开(公告)号：US5801091A

公开(公告)日：1998-09-01

申请号：US903970

申请日：1997-07-31

Applicant: Taylor R. Efland ,  Satwinder Malhi ,  Michael C. Smayling ,  Joseph A. Devore ,  Ross E. Teggatz ,  Alec J. Morton

Inventor： Taylor R. Efland ,  Satwinder Malhi ,  Michael C. Smayling ,  Joseph A. Devore ,  Ross E. Teggatz ,  Alec J. Morton

IPC: H01L23/482 ,  H01L23/528 ,  H01L29/417 ,  H01L29/78 ,  H01L21/44

CPC classification number: H01L23/5286 ,  H01L23/4824 ,  H01L29/41725 ,  H01L29/41758 ,  H01L29/7816 ,  H01L29/7835 ,  H01L2924/0002

Abstract: The device has a semiconductor chip having active circuitry in the face thereof. The circuitry has busing over it containing two conductive layers having a plurality of contacts and vias with spacings between them that alternate with respect to one another to provide current ballasting and improved switching uniformity. The spacings between the alternating contacts and vias provide regions of maximum conductor thickness and therefore reduces the busing resistance. Staggering the rows of alternating contacts and vias provides further current ballasting. A first conducting layer is used to contact and provide electrically isolated low resistive conducting paths to the various semiconductor regions while the second conducting region is used to provide selective contact to the first conductive layer, thus providing a means of busing large currents over active semiconductor area without sacrificing performance parameters.

Abstract translation: 该器件具有在其表面上具有有源电路的半导体芯片。 该电路具有引线，其中包含两个具有多个触点的导电层和在它们之间具有相互间交替的间隙的通孔，以提供电流镇流和改善的开关均匀性。 交替触点和通孔之间的间距提供最大导体厚度的区域，因此降低了阻抗。 交错的交替触点和通孔的排列提供了进一步的电流镇流。 第一导电层用于接触并提供到各种半导体区域的电隔离的低电阻导电路径，而第二导电区域用于提供与第一导电层的选择性接触，从而提供在有源半导体区域上引入大电流的装置 而不牺牲性能参数。

公开(公告)号：US5541799A

公开(公告)日：1996-07-30

申请号：US265609

申请日：1994-06-24

Applicant: Thomas A. Schmidt ,  Ross E. Teggatz ,  Joseph A. Devore

Inventor： Thomas A. Schmidt ,  Ross E. Teggatz ,  Joseph A. Devore

IPC: H03K17/082 ,  H02H7/10

CPC classification number: H03K17/0822

Abstract: In accordance with the present invention, an output current limit circuit for protecting a power MOS output device of an integrated circuit from an excessive drain current comprises a power MOS device 110, a means 30 to sense a predetermined trigger current, and a means 20 to reduce a gate-source voltage on MOS output device 110 to a predetermined approximately fixed value. A drain current I.sub.D flows through power MOS device 110 from output terminal 102 in response to the gate-source voltage. A short circuit condition may allow an excessive amount of drain current I.sub.D to flow through output terminal 102. The gate-source voltage is reduced in response to sensing the trigger current. Reducing the gate-source voltage raises a drain-source resistance of MOS device 110 and reduces drain current I.sub.D so that MOS device 110 is not damaged by the short circuit condition.

Abstract translation: 根据本发明，用于保护集成电路的功率MOS输出装置与过剩漏极电流的输出限流电路包括功率MOS器件110，感测预定触发电流的装置30和装置20至 将MOS输出装置110上的栅极 - 源极电压降低到预定的大致固定值。 漏极电流ID响应于栅极 - 源极电压从输出端子102流过功率MOS器件110。 短路状态可允许过量的漏极电流ID流过输出端子102.响应于感测触发电流，栅极 - 源极电压被降低。 降低栅极 - 源极电压会提高MOS器件110的漏极 - 源极电阻并且减少漏极电流ID，使得MOS器件110不会被短路状态损坏。

公开(公告)号：US5408141A

公开(公告)日：1995-04-18

申请号：US160

申请日：1993-01-04

Applicant: Joseph A. Devore ,  Ross E. Teggatz ,  Konrad Wagensohner

Inventor： Joseph A. Devore ,  Ross E. Teggatz ,  Konrad Wagensohner

IPC: H01L27/02 ,  H03K17/082 ,  H03K3/353

CPC classification number: H01L27/0248 ,  H03K17/0822

Abstract: An integrated power device comprises a power transistor (26) and a plurality of sense transistors (38), (40), (42), (44), and (46). Sense transistors (38), (40), (42), and (44) are constructed around the periphery of the active area occupied by power transistor (26). Sense transistor (46) is located within the interior of the active area occupied by power transistor (26) and contact is made to the necessary source region (64) of transistor (46) using a second level of metal interconnect to form a source contact (74).

Abstract translation: 集成的功率器件包括功率晶体管（26）和多个感测晶体管（38），（40），（42），（44）和（46）。 感测晶体管（38），（40），（42）和（44）围绕由功率晶体管（26）占据的有源区域的外围构成。 感测晶体管（46）位于由功率晶体管（26）占据的有效区域的内部，并且使用第二级金属互连件与晶体管（46）的必要源极区域（64）接触以形成源极接触 （74）。